Transcript Figure 9–1 The flip-flop as a storage element.

Figure 9–1
The flip-flop as a storage element.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–2
Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–3
Serial in/serial out shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–4
Four bits (1010) being entered serially into the register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–5
Four bits (1010) being serially shifted out of the register and replaced by all zeros.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–6
Open file F09-06 to verify operation.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–7
Logic symbol for an 8-bit serial in/serial out shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–8
A serial in/parallel out shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–9
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–10
The 74HC164 8-bit serial in/parallel out shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–11
Sample timing diagram for a 74HC164 shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–12
A 4-bit parallel in/serial out shift register. Open file F09-12 to verify operation.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–13
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–14
The 74HC165 8-bit parallel load shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–15
Sample timing diagram for a 74HC165 shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–16
A parallel in/parallel out register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–17
The 74HC195 4-bit parallel access shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–18
Sample timing diagram for a 74HC195 shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–19
Four-bit bidirectional shift register. Open file F09-19 to verify the operation.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–20
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–21
The 74HC194 4-bit bidirectional universal shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–22
Sample timing diagram for a 74HC194 shift register.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–23
Four-bit and 5-bit Johnson counters.
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Digital Fundamentals, 9e
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Figure 9–24
Timing sequence for a 4-bit Johnson counter.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–25
Timing sequence for a 5-bit Johnson counter.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–26
A 10-bit ring counter. Open file F09-26 to verify operation.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–27
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Digital Fundamentals, 9e
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Figure 9–28
The shift register as a time-delay device.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–29
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Digital Fundamentals, 9e
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Figure 9–30
Timing diagram showing time delays for the register in Figure 9–29.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–31
74HC195 connected as a ring counter.
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Digital Fundamentals, 9e
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Figure 9–32
Timing diagram showing two complete cycles of the ring counter in Figure 9–31 when it is initially preset to 1000.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–33
Simplified logic diagram of a serial-to-parallel converter.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–34
Serial data format.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–35
Timing diagram illustrating the operation of the serial-to-parallel data converter in Figure 9–33.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–36
UART interface.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–37
Basic UART block diagram.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–38
Simplified keyboard encoding circuit.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–39
Logic symbol for the 74HC164.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–40
Logic symbol for the 74HC194.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–41
Sample test pattern.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–42
Basic test setup for the serial-to-parallel data converter of Figure 9-33.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–43
Proper outputs for the circuit under test in Figure 9-42. The input test pattern is shown.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–44
Basic block diagram of the security system.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–45
Basic logic diagram of the security code logic.
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–46
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Digital Fundamentals, 9e
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Figure 9–47
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–48
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Digital Fundamentals, 9e
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Figure 9–49
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Digital Fundamentals, 9e
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Figure 9–50
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–51
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–52
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–53
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–54
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–55
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–56
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–57
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–58
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–59
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–60
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Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–61
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–62
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–63
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 9–64
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–65
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 9–66
Thomas L. Floyd
Digital Fundamentals, 9e
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Upper Saddle River, New Jersey 07458
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Figure 9–67
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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