Transcript Lecture 3
COMP541
Flip-Flop Timing
Montek Singh
Feb 23, 2010
1
Topics
Lab:
Feedback
VGA Display Timing Generator
Timing of flip-flops
Timing analysis of sequential systems
Clock skew
2
Input Timing Constraints
Setup time: tsetup = time
before the clock edge that
data must be stable (i.e.
not changing)
Hold time: thold = time
after the clock edge that
data must be stable
Aperture time: ta = time
around clock edge that
data must be stable (ta =
tsetup + thold)
CLK
D
tsetup thold
ta
Output Timing Constraints
Propagation delay: tpcq = time after clock edge that
the output Q is guaranteed to be stable (i.e., to stop
changing)
Contamination delay: tccq = time after clock edge
that Q might be unstable (i.e., start changing)
CLK
Q
tccq
tpcq
Dynamic Discipline
The input to a synchronous sequential circuit must be
stable during the aperture (setup and hold) time
around the clock edge.
Specifically, the input must be stable
at least tsetup before the clock edge
at least until thold after the clock edge
Implications on Design
The delay between
registers (clock period and
rate) has a minimum and
maximum delay,
dependent on the delays
of the circuit elements
Both CL and FFs
CLK
CLK
Q1
(a)
CL
R1
R2
Tc
CLK
Q1
D2
(b)
D2
Setup Time Constraint
Setup time constraint depends on max delay from R1
through the combinational logic.
And input to R2 must be stable at least tsetup before
the clock edge.
What’s min clock period?
CLK
CLK
Q1
CL
D2
R1
What’s Tc?
Tc ≥ tpcq + tpd + tsetup
tpd ≤ Tc – (tpcq + tsetup)
R2
Tc
CLK
So, clock period constrained by:
• Delay in CL
• Delay in previous regs
• Setup requirement of R2
Q1
D2
tpcq
tpd
tsetup
Hold Time Constraint
Hold time constraint depends on the minimum delay
from register R1 through the combinational logic.
The input to R2 must be stable for at least thold after
the clock edge.
CLK
CLK
Q1
R1
CL
D2
R2
CLK
Q1
D2
tccq tcd
thold
thold < tccq + tcd
tcd > thold - tccq
Timing Analysis
CLK
CLK
Timing Characteristics
tccq = 30 ps (FF contamination)
A
tpcq = 50 ps (FF propagation)
B
tsetup = 60 ps
D
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
Setup time constraint:
Tc ≥ (50 + 105 + 60) ps = 215 ps
fc = 1/Tc = 4.65 GHz
X'
X
Y'
Y
thold = 70 ps
per gate
C
tpd = 35 ps
tcd = 25 ps
Hold time constraint:
tccq + tpd > thold ?
(30 + 25) ps > 70 ps ? No!
Fixing Hold Time Violation
Add buffers to the short paths:
CLK
Timing Characteristics
CLK
tccq = 30 ps
A
tpcq = 50 ps
tsetup = 60 ps
B
D
tpd = 3 x 35 ps = 105 ps
X'
X
Y'
Y
thold = 70 ps
per gate
C
tpd = 35 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Hold time constraint:
Setup time constraint:
tccq + tpd > thold ?
Tc ≥ (50 + 105 + 60) ps = 215 ps
(30 + 50) ps > 70 ps ? Yes!
fc = 1/Tc = 4.65 GHz
Hold Time
Often FFs are designed for a hold time of zero
To avoid these tricky problems
Clock Skew
Clock doesn’t arrive at all registers at the same time
Skew is the difference between two clock edges
Examine the worst case:
guarantee that discipline is not violated for any register
many registers in a system!
delay
CLK
CLK1
CLK2
Q1
R1
t skew
CLK1
CLK2
CLK
C
L
D2
R2
Setup Time Constraint with Clock Skew
Worst case: CLK2 is earlier than CLK1
CLK1
CLK2
Q1
C
L
R1
Tc
D2
R2
Tc ≥ tpcq + tpd + tsetup + tskew
tpd ≤ Tc – (tpcq + tsetup + tskew)
CLK1
CLK2
Q1
D2
tpcq
tpd
tsetup tskew
Similar Issue w/ Hold Time
We won’t go over example
Have a look in book
14
Next Time
Read Section 3.5
Metastability
Then we’ll move on to memories
Section 5.5
Homework 3 due
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