Transcript www.jonguerber.com

Time and Statistical Information
Utilization in SAR ADCs
10110
Jon Guerber
December 4, 2012
Advisor: Dr. Un-Ku Moon
School of Electrical Engineering and
Computer Science
Oregon State University, Corvallis, OR
Oregon State Univeristy
Mixed Signal
Design
1
SAR ADC Outline
•
•
•
•
•
•
ADC Motivation
MCS and EMCS Structures
The Ternary SAR (TSAR)
Residue Shaping
The Feedback Initialized TSAR
Conclusions
2
SAR ADC Outline
• ADC Motivation
– Power Aware ADCs
– SAR ADC Benefits
•
•
•
•
•
MCS and EMCS Structures
The Ternary SAR (TSAR)
Residue Shaping
The Feedback Initialized TSAR
Conclusions
3
The Need for ADCs
10110
• Analog to Digital Conversion
– Used when digital processing units require data from analog realworld sources
– Important parameters: accuracy, bandwidth, power, cost, size …
4
ADC Motivation
1 kW
22
Resolution(bit)
20
super
1mW
audio
• Power Aware ADCs
1W
18
16
audio
14
12
1 W
10
8
Telephony
Mobile
Basestation
home
internet
cell
phones
short range
wireless
video
Wireless
LAN
UWB
6
Interconnectivity
4
1kHz 10kHz 100kHz 1MHz 10MHz100MHz 1GHz
– Power is becoming vital
in portable and medical
electronics applications
– Digital computational
computations / Joule
doubles every 1.5 years
[1| Intel 2009]
– ADC samples / Joule
doubles every 3.3 years
[2| Murmann 2010]
Signal Bandwidth
• Successive Approximation ADCs
– Provide an efficient operation in the 6-14b resolution range with
bandwidths below 100MHz
5
SAR Motivation
• SAR ADC Design
Assume box = 13kg
Initial Weight = 8kg
Is box > 8 kg?
Is box > 12 kg?
Is box > 14 kg?
Yes – Add 4 kg
Yes – Add 2 kg
No – Sub 1 kg
Box = 13 kg
– Based on feedback
subtraction
– Single comparator as
quantizer unit
– Feedback subtraction
accomplished with
passive elements
(Caps or Resistors)
• SAR Design Benefits
– Low Power: Dynamic, High efficiency
– Scalable: Good Small Process node FOM, Small Area
– Moderate Speed/Accuracy ( < 100MHz, 6-14 Bits)
Jon Guerber/6
SAR Motivation
Cap
DAC
VIN
SAR
Cap
DAC
• SAR ADC Design
DAC
Driver
DOUT
DAC
Driver
– Based on feedback
subtraction
– Single comparator as
quantizer unit
– Feedback subtraction
accomplished with
passive elements
(Caps or Resistors)
• SAR Design Benefits
– Low Power: Dynamic, High efficiency
– Scalable: Good Small Process node FOM, Small Area
– Moderate Speed/Accuracy ( < 100MHz, 6-14 Bits)
Jon Guerber/7
SAR ADC Outline
• ADC Motivation
• MCS and EMCS Structures
– SAR ADC Operation
– Switching Efficiency Optimization
•
•
•
•
The Ternary SAR (TSAR)
Residue Shaping
The Feedback Initialized TSAR
Conclusions
8
Merged Capacitor Switching SAR
VDD
VCM
DACP
2^(N-2)C
2^(N-3)C
– Sampling reference
is Vcm [1,2]
– Differentially
switches DAC
– Minimizes switching
power
– Maintains virtual
node common mode
C
VINP
VINN
2^(N-2)C
VCM
VT
SAR
2^(N-3)C
• Merged Capacitor
Switching (MCS)
C
DACN
VDD
Jon Guerber/9
MCS Switching Power
VDD VDD VCM
EVDD = (1/8)CVDD²
VDD VCM VCM
C
2C
C
C
C
C
GND GND VCM
2C
C
C
VDD GND VCM
GND VCM VCM
VCM VCM VCM
C
C
2C
EVDD = (½)CVDD²
2C
2C
EVDD = (5/8)CVDD²
C
2C
C
C
2C
C
C
GND VDD VCM
+ VIN
2C
C
GND VDD VCM
C
EVDD = (5/8)CVDD²
VCM VCM VCM
EVDD = (½)CVDD²
GND VCM VCM
2C
C
C
2C
C
C
2C
C
C
VDD GND VCM
2C
C
C
GND GND VCM
VDD VCM VCM
EVDD = (1/8)CVDD²
2C
C
C
2C
C
C
• MCS Switching
Power
– Saves switching
energy over
previous structures
– Switching efficiency
come from the direct
switching behavior
of the DAC in each
phase
– Beats the efficient of
the competing
“monotonic”
method
VDD VDD VCM
Φ1
Φ2
10
Early Reset MCS (EMCS) SAR
VDD VDD VCM
EVDD = (1/8)CVDD²
VDD VCM VCM
C
2C
C
C
C
C
GND GND VCM
2C
C
C
VCM VDD VCM
GND VCM VCM
VCM VCM VCM
C
C
2C
EVDD = (½)CVDD²
2C
2C
EVDD = (3/8)CVDD²
C
2C
C
C
2C
C
C
VCM GND VCM
+ VIN
2C
C
VCM GND VCM
C
EVDD = (3/8)CVDD²
VCM VCM VCM
EVDD = (½)CVDD²
GND VCM VCM
2C
C
C
2C
C
C
2C
C
C
VCM VDD VCM
2C
C
C
GND GND VCM
VDD VCM VCM
EVDD = (1/8)CVDD²
2C
C
C
2C
C
C
• EMCS Switching
– Uses different
switching pattern
then MCS
– On “10” and “01”
transitions, previous
DAC cap is reset
and current cap is
charged oppositely
– In each stage,
current cap is
charged to original
MSB
– Comp output
dictates resetting
VDD VDD VCM
Φ1
Φ2
11
900
0.25
800
0.2
RMS INL (LSBs)
Energy Per Code Conv. (CVdd²)
Energy and Linearity Comparison
700
600
500
MCS
EMCS
400
0.15
0.1
0.05
MCS INL
EMCS INL
0
300
0
1000
2000
Code
3000
4000
0
250
500
Code
750
1000
• MCS vs. EMCS
–
–
–
–
EMCS has 12.5% lower average switching energy (uniform input)
18.4% lower with a Gaussian input
Mathematically proven to be lower or equal energy for each code
Static linearity improvements
12
SAR Performance Enhancements
VDD
VCM
DACP
2^(N-2)C
2^(N-3)C
– How can we better
use 3-level DAC?
– Are we discarding
any valuable
information to find
the input
magnitude?
C
VINP
VINN
2^(N-2)C
VCM
VT
SAR
2^(N-3)C
• Meaningful SAR
Performance
Improvements
C
DACN
VDD
13
Comparator Delay Variation per Stage
Buffered Comparator Delay (ps)
Comparator Delay vs. Stage Voltage
550
Comparator Transfer
Function
500
450
400
VOUT t  = VG  exp  A - 1 t / τ 
350
300
250
1
3
5
7
9
11
13
SAR Stage (For Fullscale Stage Voltage)
• Comparator decision time increases linearly with stage
• Comparator delay is an indicator of input magnitude
Jon Guerber/14
SAR ADC Outline
• ADC Motivation
• MCS and EMCS Structures
• The Ternary SAR (TSAR)
– Redundancy, Speed and Power Improvements
– Stage Grouping, Skipping, Shaping
– Implementation Optimization
• Residue Shaping
• The Feedback Initialized TSAR
• Conclusions
15
Ternary SAR (TSAR) Architecture
Cap
DAC
Time
Comp
VIN
Vfs
DAC
Driver
SAR
DOUT
Digital DAC
Output Action
10
Subtract
Vfs/2 From
Input
01
Defer
Decision to
Next Stage
00
Add Vfs/
2 to Input
Vfs/4
-Vfs/4
Delay
Cap
DAC
DAC
Driver
Voltage
Comp = 1
Voltage
Comp = 0
Time
Comp = 1
Time
Comp = 0
-Vfs
• Ternary SAR (TSAR) uses comparator delay
information to create a coarse third level
– Middle level is based on input magnitude
– DAC operation is skipped for a middle code
16
TSAR Redundancy
Vfs
Digital DAC
Output Action
10
Subtract
Vfs/2 From
Input
01
Defer
Decision to
Next Stage
00
Add Vfs/
2 to Input
Vfs/4
-Vfs/4
Voltage
Comp = 1
Voltage
Comp = 0
Time
Comp = 1
Time
Comp = 0
X X
X X
X X
X X
b1 b2 b3 b4 b5
d1
d2
d3
d4
-Vfs
• TSAR Provides 1.5b/stage redundancy
– Tolerates small settling errors, fixes over-range errors
– No extra cycles or sub-radix arrays needed
– Adds just like conventional 1.5b/stage pipelined ADCs
17
TSAR Speed Enhancements
Binary
SAR
TSAR
Fixed Conversion Time
• Comparison Time Reduced in Coarse Steps
– Codes that take longer then Vfs/4 = middle code
– Comparator delay per stage is now reduced
– Worst case conversion delay shortened
18
TSAR DAC Activity Reduction
VREF Stage 1 Stage 2 Stage 3
Switch
Switch
0
No Switching
Switch
Switch
-VREF
• TSAR Switching Activity Reduction
– When the input is in the center code, no DAC cap is
switched
– Like “Multi-Comparator” Circuit but with no extra
19
voltage comparators [Liu, VLSI 2010]
TSAR Residue Shaping
Stage 1
1/2
1
1/2
1/4
0
Stage 2
-1/4 -1/2
-1
3/2
1/2
1
1/2
99.9% of Codes
Stage 9 PDF
1/4
0
-1/4 -1/2
.05%
.05%
-1
7/2
-1/512 -1/1024
Stage 3
1
1/2
0
1/1024
1/512
1/2
1/4
0
-1/4 -1/2
-1
• TSAR Residue Shaping due to 1.5b redundancy
– Improves SQNR by 6dB (Reduces DAC spread by ½)
20
– Further reduces latter stage DAC activity
TSAR Stage Grouping and Skipping
STAGE:
1
2
3
4
5
VFS
VFS
VFS
VFS
VFS
-VFS
-VFS
-VFS
-VFS
-VFS
Skip
Normal
Stage
Operation
VIN
ACTION:
Normal
Normal
Operation Operation
Don’t
Charge
Caps
• TSAR Stage Grouping
– Allows for cycle skipping (10b in 8.02 ave. cycles)
21
– Reduces number of distinct reference levels
TSAR Stage Grouping and Skipping
Stages:
1
2
Delay Reference
(As a fraction of Vfs) 1/8
3
1/32
Comparisons Per Code
Number of Comparisons
5
6
7
8
9
1/1024
• TSAR Stage
Grouping
10
9
8
7
6
5
MCS
4
4
– Grouping based on
power simulations
– Comparator power
also reduces (20%
less on average)
TSAR
3
0
250
500
Code
750
1000
22
TSAR Switching and Driver Energy
MCS
200
TSAR
150
100
50
0
Driver Energy per Code
500
Driver Capacitors Switched
Energy per Code (CVdd²)
DAC Switching Energy per Code
MCS
400
TSAR
300
200
100
0
0
250
500
Code
750
1000
0
250
500
750
1000
Code
• TSAR Energy Reductions over the MCS SAR
– Average DAC switching energy is reduced by 63.9%
23
– Average driver energy is reduced by 61.3%
TSAR Implementation
Cap
DAC
DAC
Driver
Time
Comp
VIN
SAR
DOUT
Delay
Cap
DAC
DAC
Driver
• TSAR Implemented in 0.13µm CMOS
– Delay elements consist of current starved inverters
– Input switches are bootstrapped [Dessouky JSSC 2001]
24
– Inverter based DAC Drivers
TSAR Voltage Comparator
CLK
Time
Comp
TCN
CLK
CN
VINP
CLK
VINN
CP
Time
Comp
TCP
CLK
• Voltage Comparator
– NMOS input devices, PMOS latch only
– Uses high VTH devices to read output
– Outputs directly feed time comparator
25
TSAR Time Comparator
CLK
TNP
– Gated Inverter
Based
– Device strength
based on speed
and accuracy
– Outputs fed to
SAR Registers
CP
Internal
Clock
Comparator
Operations
• Time Comparator
Voltage
Comparator
Regerating
Voltage
Comparator
Resetting
Time
Comparator
Transparent
Time Data
Latched
26
TSAR State Machine Enhancements
D
CK
bN-1 bN
RST
CK
CK
Q
CK
0
0
1
1
0
1
0
1
ETSPC EPROP
7.93fJ
3.73fJ
9.10fJ
0.02fJ
0.10fJ
3.67fJ
6.69fJ
0.02fJ
• TSPC DFF optimized for SAR ring counter
– Reduces energy on “00” state with simple asy. reset
– Saves 70% of state machine power
– Increases setup time by 50%
27
TSAR Reference 3 Calibration
01 (+1)
Mod-N
10,00 (-1)
ACC
Roll Up
Roll DN
VTREF3
Dynamic
CP
For ¼ Time Level, 50% of codes should equal “01”
• Reference Calibration Sets Third Reference
– No static power, reference stored as capacitor voltage
– First 2 references are coarse and only used for
redundancy in groups 1 and 2
– Works on the principle that latter stage distribution
become more white [Levy TCASI 2011]
28
TSAR Die Photo
Capacitor
Array
311µm
Analog Core
Capacitor
Array
180µm
[Guerber 2010]
Cap
Drivers
200µm
Calibration
x
80µm
Circuit
SAR
and
Logic
Cap
Drivers
• Layout Specs
– JAZZ 0.13µm
CMOS
– Active Area =
0.056mm² 29
TSAR Measured Results
TSAR Frequency Response
Nyquist ENOB vs. CLK Frequency
10
0
-10
Magnitude (dB)
-20
Effective Number of Bits (ENOB)
8 MHz CLK
VDD = 0.8V
FOM = 16.9fJ/C-S
-30
-40
-50
-60
-70
-80
4
8
9.5
20
9
8.5
40
8
ENOB @ 0.8V VDD
7.5
ENOB @ 1.2V VDD
-90
-100
7
0
1
2
3
Frequency (MHz)
4
4
40
Sampling Clock Frequency (MHz)
30
TSAR Measured Results
TSAR Frequency Response
Nyquist ENOB vs. CLK Frequency
10
0
-10
Magnitude (dB)
-20
Effective Number of Bits (ENOB)
8 MHz CLK
VDD = 0.8V
FOM = 16.9fJ/C-S
-30
-40
-50
-60
-70
-80
4
8
9.5
20
9
8.5
40
8
ENOB @ 0.8V VDD
7.5
ENOB @ 1.2V VDD
-90
-100
7
0
1
2
3
Frequency (MHz)
4
4
40
Sampling Clock Frequency (MHz)
31
TSAR Power Consumption
Measured TSAR Power vs. Input
TSAR Power Breakdown
310
Total TSAR Power (uW)
8%
4%
4%
290
6%
40%
270
250
38%
230
210
-50
-40
-30
-20
-10
Input Signal (dBFS)
0
Comparator
Time Comparison
SAR Logic
Cap Array/Drivers
Bootstrap Switch
Ref/CLK Gen
32
TSAR Performance Summary
CLK Freq. (MHz)
8 (12b)
8 (10b)
20 (10b)
20 (10b)
Supply (V)
0.8
1.2
0.8
1.2
Input Freq. (MHz)
4
4
10
10
Total Power (µW)
75.2
231
202
526
SNDR (dB)
61.1
59.6
53.3
55.7
SFDR (dB)
79
76.8
74.1
78.6
FOM (fJ/CS)
10.0
36.8
26.8
52.8
33
TSAR Summary
• Accuracy Improvements
– Redundancy, Residue Shaping, and Calibration
• Speed Improvements
– Reduced comp. delay and capacitor settling time
• Power Reduction
– Stage Skipping, DAC activity reduction, residue
shaping, and logic modifications
• Implementation
– Working chip demonstrated in 0.13um CMOS
34
SAR ADC Outline
•
•
•
•
ADC Motivation
MCS and EMCS Structures
The Ternary SAR (TSAR)
Residue Shaping
– SQNR Impacts
– Bounded Offset Tolerance
• The Feedback Initialized TSAR
• Conclusions
35
TSAR Residue Shaping
Stage 1
1/2
1
1/2
1/4
0
Stage 2
-1/4 -1/2
-1
3/2
1/2
1
1/2
99.9% of Codes
Stage 9 PDF
1/4
0
-1/4 -1/2
.05%
.05%
-1
7/2
-1/512 -1/1024
Stage 3
1
1/2
0
1/1024
1/512
1/2
1/4
0
-1/4 -1/2
-1
• TSAR Residue Shaping due to 1.5b redundancy
– Improves SQNR by 6dB (Reduces DAC spread by ½)
36
– Further reduces latter stage DAC activity
Pipeline ADC Residue Shaping
Stage 1
1
1/2
1/4
0
-1/4 -1/2
SQNR R-Shaped
3/4
Stage 2
1
1/2
1/4
1/4
0
 20 log10  2 1- 2-M*ST  
-1/4 -1/2
7/8
Stage 3
 SQNR R-Shaped - SQNR Traditional
1/8
Pipeline ADC PDF Residue Shaping Effect
• Residue Shaping Present in any Multi-Stage ADC
– Pipeline is similar to SAR with constant full scale range
– SQNR Improvement related to overall resolution 37
Residue Shaping ADC Design
12
ENOB (No Offset)
11.5
VFS
11
1/2
0
-1/2
10.5
VFS
VFS
3/4
1/4
-1/4
1/4
0
-1/4
10
-VFS
1x Digital Gain
9.5
Traditonal
1/2x Digital Gain
-VFS
-VFS
Proposed
9
0
0.2
0.4
0.6
0.8
Symmetric Last Stage Flash Outer
Level Magnitude as a Fraction of Vfs
1
Last Stage Reference Levels for
SQNR Improvement
• Last Stage Full-Scale Range Shrinks by ½
– Quantization noise is shaped into smaller range
– Final stage references should change
38
Residue Shaping with Other Red.
Swap PDF Halves
Stage 1
1
1/2
1/4
0
1/2
-1/4 -1/2
-1
1
1/2
1
1/4
0
-1/4 -1/2
-1
2
Stage 2a
1
Stage 2b
1/2
1
1/4
0
-1/4 -1/2
Stage 3
-1
1
1/2
1/4
0
-1/4 -1/2
-1
Extra Cycle Redundancy Residue Shaping
• Residue Shaping is not Present in Other Red.
– Extra cycle redundancy just swaps PDF halves
– Sub-Radix redundancy does change the PDF, but does
not minimize quantization noise full-scale range 39
Residue Shaping Offset Tolerance
VFS
VFS
VFS
VFS
VFS
15/32
7/32
1/32
-1/32
-7/32
1/32
-1/32
3/32
1/32
-1/32
-3/32
1/32
-1/32
1/64
0
-1/64
-15/32
-VFS
-VFS
-VFS
SAR Residue Shaping Comparator
Offset Bounds Example
VFS
VFS
-VFS
VFS
VFS
15/32
7/16
3/8
1/32
-1/32
1/16
-1/16
1/8
-15/32
-7/16
-VFS
-1/8
-3/8
-VFS
VFS
1/4
1/4
-1/4
0
-1/4
-VFS
-VFS
Pipeline Residue Shaping
Comparator Offset Bounds Example
• Sub-ADC Offset Tolerance only Slightly Reduced
– 1.5b/stage redundancy gives +/- Vfs/4 comparator offsets
– With residue shaping, early stage sub-ADC offsets tolerated
similarly, later comps. should be more accurate
40
Residue Shaping Offset Tolerance
12
11.8
11.6
ENOB
11.4
11.2
11
10.8
ADC w/ 2b Tradtional Back-end Flash
10.6
ADC w/ 2b Scaled Back-end Flash
ADC w/ 2b Scaled Back-end Flash and Ideal St. 9
10.4
ADC w/ Bounded Comparison Levels
10.2
0
0.05
0.1
0.15
0.2
0.25
3-Sigma Offset Level
• SQNR Improves even with Offsets
– Half-bit SQNR increase with no architectural changes
– Resolution improves with bounding requirements 41
followed
SAR ADC Outline
•
•
•
•
•
ADC Motivation
MCS and EMCS Structures
The Ternary SAR (TSAR)
Residue Shaping
The Feedback Initialized TSAR
– TSAR Comparison and DAC Inefficiencies
– Coarse/Fine Nestings and Recoding
• Conclusions
42
TSAR Inefficiencies
Stage 1 Stage 2
TSAR
Switching
Phases
VFS
-VFS/2
VFS/4
0
-VFS/4
-VFS/2
Switch
TSAR
Switch
No Switching
Switch
Φ1
2C
Φ2
C
Φ3
C
VG
TSAR Comparator Sizes
Sized
Stage Comparator
Accuracy
1
2
3
13b
13b
13b
Switch
-VFS
VFS
Switch Optimal
-VFS/2
VFS/4
0
Switch
No Switching
-VFS/4
-VFS/2
-VFS
Optimal
Switching
Phases
Switch
Φ1
2C
Φ1
C
Φ1
C
VG
Optimal Comparator Sizes
Sized
Stage Comparator
Accuracy
1
2
3
3b
4b
5b
Switch
Driver Activity
DAC Switching
Comparator Energy
4
FITSAR Block Diagram
7b TSAR
Fine DAC LSBs
(R2R Based)
Fine DAC MSBs
(Cap Based)
Recoded
Coarse
DAC
VIN
Data Timed 6b
Binary SAR
• FITSAR Architectural Benefits:
– Nested coarse ADC structure (Comparator Energy)
– Fine DAC bit recoding (DAC Activity and Switching)
– Fine DAC feedback initialization (DAC Activity and Switching)
Jon Guerber/44
FITSAR Nesting
Cap
DAC
DAC
Driver
Coarse SAR
Time
Comp
VIN
SAR
DOUT
Delay
Cap
DAC
DAC
Driver
• Multi-Stage SAR ADCs
– Pipelined: Requires Inter-stage Amplification, Decouples
Fine/Corse Bits
– Split Comparator: No Inter-stage Amplification, Coupled
Fine/Corse Bits
– Nested: No Amplification, Decouples Fine/Corse Bits
45
Feedback TSAR Recoding
DAC Recoding
COUT
000
001
010
011
100
101
110
111
F1 F2
VDD VDD
VDD VCM
VCM VDD
VCM VCM
VCM VCM
VCM GND
GND VCM
GND GND
DAC Logic
VFS
C1
C2
F1(VDD)
C1b
C2b
F1(GND)
C1
C3
F2(VDD)
C1b
C3b
F2(GND)
FITSAR DAC Movement
0
0
1/4 1/8
VCM
0
1/32
Φ1 Φ1 Φ1 Φ1 Φ1 Φ1
EC = 7.71*(CVDD²)
-VFS
• FITSAR Recoding optimizes DAC “Windowing”
– Converts binary coarse output to optimal ternary codes
– Maintains redundancy and residue shaping
Jon Guerber/46
– Implemented with simple logic blocks
Feedback Initialization
GND to VDD
Switching Phase
Φ1
2C
Φ1
2C
Φ1
2C
Φ2
C
Φ3
C
Φ1
Φ2
C
C
Φ1
Φ1
C
C
Switching Energy
 V 
 V  5
EVDD = VDD 2C  DD  + C  DD   = CVDD2
 4  4
  2 
 
3
 3
EVDD = VDD 3C  VDD - VDD   = CVDD2
4
 4
 
E VDD = 0
Floating 
• Fine DAC switching is grouped
– All codes from the coarse SAR are switched to the fine
in a single phase
– Large energy savings due to large fine DAC and small
Jon Guerber/47
coarse DAC
DAC Switching Comparison
MCS DAC
Movement
VFS
1/4
TSAR DAC
Movement
VFS
1/32
1/8
0
1/2
VCM
1/8 1/16
1/64
VCM
Φ1 Φ2 Φ3 Φ4 Φ5 Φ6
1/2
0
0
0
1/32
VCM
1/4 1/8
0
1/32
EC = 7.71*(CVDD²)
EC = 14.09*(CVDD²)
-VFS
0
Φ1 Φ1 Φ1 Φ1 Φ1 Φ1
Φ1 Φ2 Φ3 Φ4 Φ5 Φ6
EC = 23.32*(CVDD²)
-VFS
FITSAR DAC
Movement
VFS
-VFS
• Time-Based DAC Movement Comparison
–
–
–
–
MCS requires the DAC to switch in each phase, high activity
TSAR eliminates DAC switching for small virtual ground inputs
FITSAR optimizes switching operation to only be in one direction
FITSAR also switching in one phase, reducing crossover losses
Jon Guerber/48
FITSAR Switching and Driver Energy
MCS
FIT
800
TSAR
700
600
500
400
300
200
100
0
Capacitors Switched per Code Conversion
Energy Per Code Conversion (CVdd²)
900
1000
800
600
400
200
FIT
TSAR
0
0
1000
2000
Code
3000
4000
0
2000
Code
4000
• FITSAR Optimally Reduces Fine DAC Switching
for 3 Levels
– DAC Power Reduced 86% over MCS (61% over TSAR)
– Driver activity Reduced 74% over MCS (34% over TSAR)
49
FITSAR Comparator Activity Red.
12
No. Eqv. Fine Comparisons Per Code
No. Eqv. Fine Comparisons Per Code
12
11
10
9
8
7
6
5
4
MCS
3
TSAR
2
MCS
11
FIT
10
9
8
7
6
5
4
3
2
0
1000
2000
Code
3000
4000
0
1000
2000
Code
3000
4000
• Fine Comparator Activity Reduced over TSAR
– MCS: 12 Comps/Code
– TSAR: 10.2 Comps/Code (15% energy reduction over MCS)
– FITSAR: 5.6 Comps/Code (53% energy reduction over MCS)
50
Comparator Implementation
CLK
CLK
CN
CP
VINP
CLK
CLK
CN
CP
VINP
CLK
CLK
CLK
CLK
Strongarm
• Coarse ADC Comp
– Lower Accuracy (8-bit
noise)
– High Speed
– No Static Power
VINN
P-Latch
• Fine ADC Comp
– Higher Accuracy (14-bit
noise)
– Med Speed
– Static Power when not
Jon Guerber/51
Reset
Coarse ADC: EMCS
VDD VDD VCM
EVDD = (1/8)CVDD²
VDD VCM VCM
2C
2C
EVDD = (½)CVDD²
C
C
2C
C
C
2C
C
C
GND GND VCM
C
VCM VDD VCM
EVDD = (3/8)CVDD²
C
C
C
GND VCM VCM
VCM VCM VCM
2C
2C
C
C
2C
C
C
•
EMCS Coarse ADC
–
Output is
automatically
recoded
Higher coarse
linearity
Lower switching
power, fewer latches
–
–
VCM GND VCM
+ VIN
C
VCM GND VCM
C
EVDD = (3/8)CVDD²
VCM VCM VCM
EVDD = (½)CVDD²
2C
C
C
VGP
GND VCM VCM
2C
C
C
2C
C
C
Q
ER Merged
Capacitor
Switching
C
C
VDD VCM VCM
VGN
D
R
Q
R
C
ST
2C
C
C
VDD VDD VCM
DN1
DFF
D
Q
DFF
EVDD = (1/8)CVDD²
UP2
DFF
DFF
GND GND VCM
C
Q
B
VCM VDD VCM
2C
D
R
R
D Q
2C
UP1
DFF
A
MUX
2C
D
Φ1
D
Q
DFF
R
R
D Q
DN2
DFF
Φ2
D
Q
Φ3
DFF
CK
EMCS Implementation
52
FITSAR Comparator Gating
CLK
COMP
CLK
PH(n)
DN(n+1) UP(n+2)
UP(n+1)
PH(n+1)
DN(n+2)
PH(n+2)
Comparator Clock Gating Circuit
• Comparator Clock Gated by Stage Outputs
– Replaces Skipping for faster critical delay logic path
– Gates clock to comparator based on state outputs
53
FITSAR R2R DAC Nesting
F1
FITSAR Nested
DAC
F2
2R
2R
F3
2R
VCM
2R
FN
VINP
2(N-5)C
R
F(N-1)
2(N-6)C
R
F4
2C
C
• SAR DAC arrays are often Mismatch Limited
– Can reduce overall DAC by calibration or Nesting
– Now Thermal noise limited, 4x-ish reduction
– No “Coupling capacitor” problems
54
Ternary R2R DAC
2R
B3
B2
2R
2R
2R
GND
R
R
R
Traditional R2R DAC
T3
2R
T2
T1
2R
2R
B1/2
+
2R
R
R
B1b/2
2R
2R
VOUT
-
2R
T3b
T2b
T1b
3-level R2R DAC
•
2-Level
3-Level
1.4
VOUT
2R
1.6
B1
Normalized Power (W/R)
B4
1.2
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
60
Code
3-level R2R DAC
–
–
3-level DAC has a 79% power improvement over the traditional 2-level
Jon Guerber/55
Provides linearity improvements by eliminating major transition
FITSAR Prototype Layout
Fine
DAC
Buffers
Scan and
Trim Logic
Fine Cap DAC
VINN
VINP
Input Switches
R2R
DAC
and
Buffers
Bootstrapping
Coarse DAC
Circuit
Fine
Internal Ref
Logic
Coarse Logic and
FN
CMP CLK GEN Buf and State
Comparator
Machine
Bootstrapping
Coarse DAC
Circuit
Fine
DAC
Buffers
Digital
Buffers
Clock Gen
and Buffer
Digital
Buffers
FITSAR Die Photo
•
Fine Cap DAC
R2R
DAC
and
Buffers
FITSAR Floorplan
Scan and
Trim Logic
FITSAR Prototype Layout
–
–
–
Area is 0.06mm²
Fabricated in National 0.13u CMOS
Psudo-differential layout
Jon Guerber/56
FITSAR Transistor Level Simulations
Spec/Date
FITSAR 1.2V FITSAR 0.8V
TSAR 0.8V
ENOB
11.76
11.18
9.85
Frequency
50 MHz
10 MHz
8 MHz
Power
362 uW
32.8 uW
75.2 uW
Process
(VDD)
Optimos2
(1.2)
Optimos2
(0.8)
Jazz 0.13u
(0.8)
FOM
2.08 fJ/CS
1.41 fJ/CS
10.0 fJ/CS
57
SAR ADC Outline
•
•
•
•
•
•
SAR Motivation
MCS and EMCS Structures
The Ternary SAR (TSAR)
Residue Shaping
The Feedback Initialized TSAR
Conclusions
58
Published Work
•
J. Guerber, H. Venkatram, M. Gande, and U. Moon, “A Ternary R2R DAC Design
for Improved Energy Efficiency,” Elec. Letters, Submitted Dec. 2012.
•
J. Guerber, M. Gande, H. Venkatram, A. Waters, U. Moon, “A 10b Ternary SAR
ADC with Quantization Time Information Utilization,” IEEE J. Solid State Circuits.
Nov. 2012.
•
J. Guerber, M. Gande, U. Moon, “The Analysis and Application of Redundant MultiStage ADC Resolution Improvements Through PDF Residue Shaping,” IEEE Trans.
Circuits Syst. I, Fundam. Theory Appl., Aug. 2012.
•
J. Guerber, H. Venkatram, T. Oh, U. Moon, “Enhanced SAR ADC Energy Efficiency
from the Early Reset Merged Capacitor Switching Algorithm,” IEEE Int. Symp.
Circuits Syst., May 2012.
•
J. Guerber, M. Gande, H. Venkatram, A. Waters, U. Moon, “A 10b Ternary SAR
ADC with Decision Time Quantization Based Redundancy,” IEEE Asian Solid-State
Circuits Conf. Nov. 2011, pp. 63-65.
59
Conclusions
• Energy Efficient SAR Architectural Changes
–
–
–
–
Switching efficiency though EMCS, TSAR, and FITSAR
Comparison Reduction through TSAR and FITSAR
Stage Skipping and grouping though TSAR
Recoding and Nesting with FITSAR
• ADC Sample Rate Enhancements
– Comparator speed enhancements though TSAR
– Coarse SAR speed increase in FITSAR
• Accuracy Improvements
– Residue shaping SQNR increases in TSAR, FITSAR, and pipelined
structures
– 1.5b/stage redundancy shown in TSAR and FITSAR
60
Questions
61
Backup Slides
Residue Shaping with Sub-Radix
TSAR Core Timing Diagram
TSAR Capacitor Layout
TSAR Quantizer Schematic
TSAR State Machine Logic
FITSAR Core Blocks
FITSAR Coarse Logic (EMCS)
62
Residue Shaping with Sub-Radix
Stage 4
Stage 1
4
3
½
2
1.4
.70
0
-.70
-14
.24
Stage 2
.17 .14
1
.70
1
.41
.41
2
.29 .24
0
-.41
0
-.70
-.41
-.14 -.17 -.24
4
4
3
-.24 -.29
.06
Stage 5
5 4 5
Stage 3
0
.06
.14
.08 .06
3
.01 0 -.01 -.06 -.08
-.14
Sub-Radix Redundancy Residue Shaping
• Residue Shaping is not Present in Sub-Radix
– PDF does shape, but does not minimize full-scale range
63
due to effective 1 bit quantization per stage
TSAR Core Timing Diagram
Internal Clock
Voltage Comp. Op:
Time Latch Op:
Falling Edge Set By
Time Reference
Regenerating
Transparent
Resetting
Data Latched
Virtual Ground
Nodes
Internal SAR
Phase
Phase N
Time
Reference
Ref. N
Phase N+1
Ref. N+1
64
TSAR Capacitor Layout
9
8
9
9
9
7
9
8
8
9
7
9
9
9
8
9
8
9
7
9
8
9
8
9
9
8
9
8
9
7
9
8
9
7
9
8
9
8
9
7
7
9
8
9
8
9
7
9
9
9
8
9
6
9
8
9
9
8
9
6
9
8
9
9
9
8
9
6
9
5
9
8
8
9
5
9
6
9
8
9
7
9
8
9
5
9
7
9
9
7
9
5
9
8
9
7
9
8
9
8
9
7
4
6
6
4
7
9
8
9
8
9
8
9
7
9
8
9
6
3
1
6
9
8
9
7
9
8
8
9
7
9
8
9
6
2
3
6
9
8
9
7
9
8
9
8
9
8
9
7
4
6
6
4
7
9
8
9
8
9
7
9
8
9
5
9
7
9
9
7
9
5
9
8
9
7
9
8
9
6
9
5
9
8
8
9
5
9
6
9
8
9
9
9
8
9
6
9
8
9
9
8
9
6
9
8
9
9
9
7
9
8
9
8
9
7
7
9
8
9
8
9
7
9
8
9
7
9
8
9
8
9
9
8
9
8
9
7
9
8
9
8
9
9
9
7
9
8
8
9
7
9
9
9
8
9
• Layout in Unit
Elements
– Common
centroid to fix
first order
gradients
– Maintain average
distance to center
– Digital inputs all
enter from right
– Virtual ground
exits on left
65
TSAR Quantizer Schematic
CKRST
CKRST
CKSET
3x
2x
12x
2x
6x
RST
Current Starved
VGP
VGN
3x
SAR
Registers,
Phase
selector
and
Reference
selector
CKSET
CKRST
CKSET
66
TSAR State Machine Logic
UP2
DN2
1x
R
S0
CK
D Q
S1
UP3
DN3
S2
S3
D Q
D Q
D Q
CK DFF CK DFF
DFF
DFF
Q
1x
CK
Q
CK
Q
S4
Q
SN2
UP5
DN5
CK
S5
UP6
DN6
S6
UP7
DN7
S7
UP8
DN8
S8
D Q
D Q
D Q
D Q
D Q
DFF
DFF
DFF
DFF
DFF
Q
CK
Q
CK
Q
CK
Q
EOC
SN3
CK
Q
S9
D Q
DFF
CK
Q
67
FITSAR Core Blocks
REFOUT (To Internal CLK Gen)
9x
6x
10x/10x
PIN
REF1
9x
P9
CKB
RB
6x
10x/10x
REF2
9x
10x/10x
6x
REF3
P10
CKB
9x
EOC
CKB
CKB
P9
PIN
10x/10x
6x
REF4
CKB
P10
Reference Mux
CLK GATE
RST
EOC
REF
CMP
TD
Internal Clock Generator
68
FITSAR Coarse Logic (EMCS)
VGP
MUX
A
S
Q D
D Q
DLT
DLT
R
R
U1
D1 Q U2
D2
DLT
UF1
R
AOI
B
UF2
D1 Q U3
D2
DLT
R
AOI
D1 Q U4
D2
UF3
DLT
R
AOI
D1 Q U5
D2
UF4
DLT
R
AOI
UF5
AOI
VGN
RB
CLK
P7
R
DF1
DLT
D Q
D1
R
DLT
D2
D1 Q
DF2
D2
R
DLT
D2
D1 Q
DF3
R
DLT
D2
D1 Q
D3
DF4
R
DLT
D2
D1 Q
D4
DF5
D5
P5
P5
D Q
D Q
D Q
D Q
DFF
DFF
DFF
DFF
DFF
R
R
R
R
R
R
POUT
D Q
P7B
69
FITSAR Fine Logic (Gating)
Gate
5x
3x
3x
5x
3x
3x
FCP
D Q
DLT
CKM
U6
Qb
R
D Q
DLT
U7
Qb
R
D Q
DLT
U8
Qb
R
D Q
DLT
U9
Qb
R
D Q
DLT
U10
Qb
R
R
R
Qb
R
Qb
DLT
P7
D Q
R
Qb
DLT
D6
D Q
R
Qb
DLT
D7
D Q
R
Qb
DLT
D8
D Q
DLT
D9
D Q
D10
FCN
PIN D Q
DFF
D Q
D Q
D Q
D Q
DFF
DFF
DFF
DFF
R
R
R
R
R
EOC
70
TSAR Layout Floorplan
Calibration
Fine Cap DAC
DAC
Buffers
Boot Cap
VINN
VINP
Boot Cap
Input Switches
Digital
Buffers
Bootstrapping
Logic
Fine
Ref Logic and
CMP Internal
/ TC CLK GEN Buf
State
Machine
Bootstrapping
Logic
Clock Gen
and Buffer
Digital
Buffers
Fine Cap DAC
DAC
Buffers
Calibration
71
TSAR Prototype Test Setup
Power
Supply
AGe3631
LDO
ADJ
ADP1708
100n/10u 100n
RP50k
10u
I-Meter
Fluke45
3
SUP1
SUP2-6
RF Signal
Generator
HP 8665A
BP Filter
50
VCM
Output 10
Logic
Buffers
Analyzer
SN74AVC
TLA720
MATLAB
Analysis
SUP SCAN
VIP
TSAR
10n
DO
VIN
CLK REFS
ADT1-1WT
8
RF Signal
Generator
AG 8643A
AVR
Studio
6
5
SMA
AVR uC 6 AVR Prog
Tiny84
ISPMKII
7
10
REF2-8
100n
RP50k
BP Filter
50
RPOT
ADA
4004
10u 100n
RP1k
Bandgap
MAX6126
100n/10u
Power
Supply
AGe3631
REF1
72
References I
1.
2.
3.
4.
V. Hariprasath, J. Guerber, S.-H. Lee, and U. Moon, “Merged
capacitor switching based SAR ADC with highest switching
energy-efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 29,
2010.
Y. Zhu, C.-H. Chan, et al., “A 10b 100MS/s reference-free SAR
ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp.
1111-1121, Jun. 2010.
J. Yang, T. Naing, and R. Brodersen, “A 1 GS/s 6b 6.7mW
successive approximation ADC using asynchronous
processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp.
1469-1478, Aug. 2010.
C.-C. Liu, S.-J. Chang, et al., “A 1V 11fJ/conversion-step 10b
10MS/s asynchronous SAR ADC in 0.18um CMOS,” IEEE
Symp. On VLSI Circuits, June 2010, pp. 241-242.
73
References II
5.
6.
B. Levy, “A propagation analysis of residual distribution in
pipeline ADCs,” IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., vol. 58, no. 10, pp. 2366-2376, Oct. 2011.
M. Dessouky, A. Kaiser, “Very low-voltage digital-audio ΔΣ
modulator with 88-dB dynamic range using local switch
bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3,
Mar. 2001.
74