Transcript CHAPTER 3 MEMORY MANAGEMENT PART 2

CHAPTER 3
MEMORY MANAGEMENT
PART 2
by Uğur Halıcı
3.3 Paging
1
Logical
memory
PAGE TABLE
In paging, the OS
divide the physical page frame Attributes
memory into frames
0
4
which are blocks of
1
3
small and fixed size
2
1
3
5
Physical
memory
3.3 Paging
2
Logical
memory
PAGE TABLE
In paging, the OS
divide P0
the physical page frame Attributes
memoryP1
into frames
0
4
which are
1
3
P2 blocks of
small and fixed size
2
1
P3
3
5
Physical
memory
f0
f1
f2
f3
f4
f5
3.3 Paging
3
Logical
memory
OS divides
also the
PAGE
TABLE
logicalAttributes
memory
page frame
(program) into pages
0
4
which are blocks of
1 size3equal to frame
2
1 size.
3
5
Physical
memory
f0
f1
f2
f3
f4
f5
3.3 Paging
4
Logical
memory
P0
P1
P2
P3
OS divides
also the
PAGE
TABLE
logicalAttributes
memory
page frame
(program) into pages
0
4
which are blocks of
1 size3equal to frame
2
1 size.
3
5
Physical
memory
f0
f1
f2
f3
f4
f5
3.3 Paging
5
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
Physical
memory
frame Attributes
4
3
1
5
The OS uses a page table to map program pages to
memory frames.
f0
f1
f2
f3
f4
f5
3.3 Paging
6
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
frame Attributes
4
3
1
5
Physical
memory
P0
The OS uses a page table to map program pages to
memory frames.
f0
f1
f2
f3
f4
f5
3.3 Paging
7
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
frame Attributes
4
3
1
5
Physical
memory
P1
P0
The OS uses a page table to map program pages to
memory frames.
f0
f1
f2
f3
f4
f5
3.3 Paging
8
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
frame Attributes
4
3
1
5
Physical
memory
P2
P1
P0
The OS uses a page table to map program pages to
memory frames.
f0
f1
f2
f3
f4
f5
3.3 Paging
9
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
frame Attributes
4
3
1
5
Physical
memory
P2
P1
P0
P3
The OS uses a page table to map program pages to
memory frames.
f0
f1
f2
f3
f4
f5
3.3 Paging
10
Logical
memory
P0
P1
P2
P3
PAGE TABLE
page
0
1
2
3
Physical
memory
frame Attributes
4
3
1
5
Paging permits a program to allocate noncontiguous
blocks of memory
P2
P1
P0
P3
f0
f1
f2
f3
f4
f5
3.3 Paging
11

Page size (S) is defined by the hardware.
 Generally
page size is chosen as a power of 2 such
as 512 words/page or 4096 words/page etc.

With this arrangement, the words in the program have
an address called as logical address. Every logical
address is formed of <p,d> pair
3.3 Paging
12

Logical address: <p,d>
p
is page number
p = logical address div S
d
is displacement (offset)
d = logical address mod S
3.3 Paging
13

When a logical address <p, d> is
generated by the processor, first the frame
number f corresponding to page p is
determined by using the page table and
then the physical address is calculated as
(f*S+d) and the memory is accessed.
3.3 Paging
14
Logical
address
Physical
address
p
f
d
page frame
d
attr
d
d
p
f
p
logical
memory
f
physical
memory
3.3 Paging
15
Example 3.2





Consider the following information to form a physical memory
map.
Page Size = 8 words  d : 3 bits
Physical Memory Size = 128 words
= 128/8=16 frames  f : 4 bits
Assume maximum program size is 4 pages  p : 2 bits
A program of 3 pages where P0  f3; P1  f6; P2  f4
Logical memory
Physical memory
…
Word 0
16
Word 1
…
Page 0
Word 0
(P0)
Word 1
Word 7
PAGE TABE
…
Word 8
Page Frame
Word 7
Word 9
…
Page 1
0
3
Word 16
(P1)
1
6
Word 17
2
4
…
Word 15
Word 16
Word 17
…
…
Frame 3
(f3)
Frame 4
(f4)
Word 23
Page 2
(P2)
…
…
Word 23
Word 8
Word 9
…
Frame 6
(f6)
Word 15
…
…
3.3 Paging
17
Program
Line
Word 0
Word 1
…
Word 7
Word 8
Word 9
…
Word 15
Word 16
Word 17
…
Word 23
3.3 Paging
18
Program
Line
Word 0
Logical
Address
00 000
Word 1
00 001
…
…
Word 7
00 111
Word 8
01 000
Word 9
01 001
…
…
Word 15
01 111
Word 16
10 000
Word 17
10 001
…
…
Word 23
10 111
3.3 Paging
19
Program
Line
Word 0
Logical
Address
00 000
Offset
Word 1
00 001
001
…
…
…
Word 7
00 111
111
Word 8
01 000
000
Word 9
01 001
001
…
…
…
Word 15
01 111
111
Word 16
10 000
000
Word 17
10 001
001
…
…
…
Word 23
10 111
111
000
3.3 Paging
20
Program
Line
Word 0
Logical
Address
00 000
Offset
000
Page
Number
00
Word 1
00 001
001
00
…
…
…
…
Word 7
00 111
111
00
Word 8
01 000
000
01
Word 9
01 001
001
01
…
…
…
…
Word 15
01 111
111
01
Word 16
10 000
000
10
Word 17
10 001
001
10
…
…
…
…
Word 23
10 111
111
10
3.3 Paging
21
Program
Line
Word 0
Logical
Address
00 000
Offset
Word 1
000
Page
Number
00
Frame
Number
0011
00 001
001
00
0011
…
…
…
…
…
Word 7
00 111
111
00
0011
Word 8
01 000
000
01
0010
Word 9
01 001
001
01
0010
…
…
…
…
…
Word 15
01 111
111
01
0010
Word 16
10 000
000
10
0000
Word 17
10 001
001
10
0000
…
…
…
…
…
Word 23
10 111
111
10
0100
3.3 Paging
22
Program
Line
Word 0
Logical
Address
00 000
Offset
Word 1
000
Page
Number
00
Frame
Number
0011
Physical
Address
0011 000
00 001
001
00
0011
0011 001
…
…
…
…
…
…
Word 7
00 111
111
00
0011
0011 111
Word 8
01 000
000
01
0010
0110 000
Word 9
01 001
001
01
0010
0110 001
…
…
…
…
…
…
Word 15
01 111
111
01
0010
0110 111
Word 16
10 000
000
10
0000
0100 000
Word 17
10 001
001
10
0000
0100 001
…
…
…
…
…
…
Word 23
10 111
111
10
0100
0100 111
3.3 Paging
23


Every access to memory should go through the page
table. Therefore, it must be implemented in an
efficient way.
How to Implement The Page Table?
 Using
fast dedicated registers
 Keep the page table in main memory
 Use content-addressable associative registers
Using fast dedicated registers
24


Keep page table in fast dedicated registers. Only
the OS is able to modify these registers.
However, if the page table is large, this method
becomes very expensive since requires too many
registers.
Using fast dedicated registers
25
PTLR: Page Table Length Register
logical address
p
d
physical address
YES
P<PTLR
NO
access
PT in
registers
rat
ERROR
Effective Memory Access Time
emat=rat+mat
f
d
access
memory
mat
Keep the page table in main memory
26


In this second method, the OS keeps a page table in
the memory, instead of registers.
For every logical memory reference, two memory
accesses are required:
1.
2.

To access the page table in the memory, in order to find
the corresponding frame number.
To access the memory word in that frame
This is cheap but a time consuming method.
Keep the page table in main memory
27
PTBR: Page Table Base Register
PTLR: Page Table Length Register
logical address
p
d
YES
P<PTLR
NO
Access PT
entry
in Memory
at address
PTBR + p
mat
ERROR
Effective Memory Access Time:
emat=mat+mat=2mat
physical address
f
d
access
memory
mat
Use content-addressable associative registers
28





This is a mixing of first two methods.
Associative registers are small, high speed registers
built in a special way so that they permit an
associative search over their contents.
That is, all registers may be searched in one
machine cycle simultaneously.
However, associative registers are quite expensive.
So, a small number of them should be used.
In the overall, the method is not-expensive and notslow.
Use content-addressable associative registers
29
physical address
logical address
p
f
d
Found?
d
Yes (HIT)
No (MISS)
P<PTLR
No
Yes
search
PT in AR
rat
ERROR
Access PT
entry
in Memory
at address
PTBR + p
physical address
f
d
mat
Effective Memory Access Time:
access
memory
mat
h: hit ratio
Emat=h *ematHIT + (1-h) * ematMISS =h(rat+mat)+(1-h)(rat+mat+mat)
Use content-addressable associative registers
30




Assume we have a paging system which uses associative
registers. These associative registers have an access time of 30
ns, and the memory access time is 470 ns. The system has a hit
ratio of 90 %.
rat=30 ns
mat=470ns
h=0.9
Use content-addressable associative registers
31
rat=30 ns, mat=470ns, h=0.9



Now, if the page number is found in one of the associative
registers, then the effective access time:
ematHIT = 30 + 470 = 500 ns.
Because one access to associative registers and one access to
the main memory is sufficient.
Use content-addressable associative registers
32
rat=30 ns, mat=470ns, h=0.9



On the other hand, if the page number is not found in
associative registers, then the effective access time:
ematMISS = 30 + (470+470) = 970 ns.
Since one access to associative registers and two accesses to
the main memory are required.
Use content-addressable associative registers
33
rat=30 ns, mat=470ns, h=0.9
ematHIT = 500 ns, ematMISS = 970 ns.

Then, the emat is calculated as follows:
emat= h *ematHIT + (1-h) * ematMISS
= 0.9 * 500 + 0.1 * 970
= 450 + 97 = 547 ns
Sharing Pages
34



Sharing pages is possible in a paging system, and is an
important advantage of paging.
It is possible to share system procedures or programs, user
procedures or programs, and possibly data area.
Sharing pages is especially advantageous in time-sharing
systems.
Sharing Pages
35



A reentrant program (non-self-modifying code = read only)
never changes during execution.
So, more than one process can execute the same code at the
same time.
Each process will have its own data storage and its own copy
of registers to hold the data for its own execution of the
shared program.
Sharing Pages
36

Example 3.4

Consider a system having page size=30 MB.



There are 3 users executing an editor program which is 90 MB (3 pages) in
size, with a 30 MB (1 page) data space.
To support these 3 users, the OS must allocate 3 * (90+30) = 360 MB
space.
However, if the editor program is reentrant (non-self-modifying code =
read only), then it can be shared among the users, and only one copy of the
editor program is sufficient. Therefore, only 90 + 30 * 3 = 180 MB of
memory space is enough for this case
37
P0
P1
P2
P3
User-1
e1
e2
e3
data1
PT-1
Page#
0
1
2
3
Frame#
8
4
5
7
P0
P1
P2
P3
User-2
e1
e2
e3
data2
PT-2
Page#
0
1
2
3
Frame#
8
4
5
12
P0
P1
P2
P3
User-3
e1
e2
e3
data3
PT-3
Page#
0
1
2
3
Frame#
8
4
5
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
e2
e3
data1
e1
38
P0
P1
P2
P3
User-1
e1
e2
e3
data1
PT-1
Page#
0
1
2
3
P0
P1
P2
P3
User-2
e1
e2
e3
data2
PT-2
Page#
0
1
2
3
P0
P1
P2
P3
User-3
e1
e2
e3
data3
PT-3
Page#
0
1
2
3
Frame#
8
4
5
7
Frame#
8
4
5
12
Frame#
8
4
5
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
e2
e3
data1
e1
data 2
39
P0
P1
P2
P3
P0
P1
P2
P3
P0
P1
P2
P3
User-1
e1
e2
e3
data1
User-2
e1
e2
e3
data2
User-3
e1
e2
e3
data3
PT-1
Page#
0
1
2
3
PT-2
Page#
0
1
2
3
PT-3
Page#
0
1
2
3
Frame#
8
4
5
7
Frame#
8
4
5
12
Frame#
8
4
5
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
e2
e3
data1
e1
data3
data 2
40
P0
P1
P2
P3
User-1
e1
e2
e3
data1
User-2
PT-1
Page#
0
1
2
3
PT-2
User 2 terminates:
P0
e1
Data2
page
is removed Page#
P1
e2
from
memory,
but editör 0
P2
1
pagese3
remain..
P3
P0
P1
P2
P3
data2
User-3
e1
e2
e3
data3
Frame#
8
4
5
7
2
3
Frame#
8
4
5
12
PT-3
Page#
0
1
2
Frame#
8
4
5
3
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
e2
e3
data1
e1
data3
41
P0
P1
P2
UserP31
User-1
e1
e2
e3
terminates:
data1
data1 is also removed
from memory.
P0
P1
P2
P3
P0
P1
P2
P3
User-2
e1
e2
e3
data2
User-3
e1
e2
e3
data3
PT-1
Page#
0
1
2
3
Frame#
8
4
5
7
PT-2
Page#
0
1
2
3
Frame#
8
4
5
12
PT-3
Page#
0
1
2
Frame#
8
4
5
3
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
e2
e3
e1
data3
42
P0
P1
P2
P3
User-1
e1
e2
e3
data1
PT-1
Page#
0
1
2
3
Frame#
8
4
5
7
P0
P1
P2
P3
User-2
e1
e2
e3
data2
PT-2
Page#
0
1
2
3
Frame#
8
4
5
12
When
User 3 terminates:
User-3
PT-3
Data-3
and also editor
P0
e1
Page#
segments
are
removed
P1
e2
0
from memory. 1
P2
e3
P3
data3
2
Frame#
8
4
5
3
10
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
f10
f11
f12
f13
f14
f15
Physical
Memory
OS
OS
OS
3.4 Segmentation
43





In segmentation, programs are divided into variable size
segments, instead of fixed size pages.
This is similar to variable partitioning, but programs are
divided to small parts.
Every logical address is formed of a segment name and an
offset within that segment.
In practice, segments are numbered.
Programs are segmented automatically by the compiler or
assembler.
3.4 Segmentation
OS
44

For example, a C compiler may create segments for:
 the code of each function
 the local variables for each function
 the global variables.
main
Func 1
Func 2
main
Func 1
Func 2
Data 1
Data 2
Data 1
Data 2
Data 3
Logical memory
Data 3
Physical memory
3.4 Segmentation
45

For logical to physical address mapping, a segment table is
used. When a logical address <s, d> is generated by the
processor:
1.
2.
3.
Base and limit values corresponding to segment s are determined
using the segment table
The OS checks whether d is in the limit. (0  d < limit)
If so, then the physical address is calculated as (base + d), and the
memory is accessed.
3.4 Segmentation
OS
46
Logical address
s
No
d
ERROR
0≤d
<limit
base
Segment Table
d
segment s
Yes
seg. #
limit
base
attr
acess
the word at
physical address
= base + d
Physical memory
3.4 Segmentation
47
Example 3.5
Generate the memory map according to the given
segment table. Assume the generated logical
address is <1,1123>; find the corresponding
physical address.

Segment
Limit
Base
0
1
2
3
1500
200
700
2000
1000
5500
6000
3500
3.4 Segmentation
0
OS
48
Segment
Limit
Base
1000
0
1500
1000
1
200
5500
2
700
6000
2500
3
2000
3500
3500
s0
s3
1500
2000
5500
s1
s2
200
5700
6000
700
6700
Physical memory
3.4 Segmentation
0
OS
49
Segment
Limit
Base
1000
0
1500
1000
1
200
5500
2
700
6000
2500
3
2000
3500
3500
s0
s3
1500
2000
5500
Logical address: <3,1123>
s=3, d=1123
Check if d<limit? 1123<2000, OK
Physical address= base+d=3500+1123=4623
s1
s2
200
5700
6000
700
6700
Physical memory
3.4 Segmentation
0
OS
50
Segment
Limit
Base
1000
0
1500
1000
1
200
5500
2
700
6000
3
2000
3500
s0
1500
Base=
3500
2500
3500
s3
2000
5500
Logical address: <3,1123>
s=3, d=1123
Check if d<limit? 1123<2000, OK
Physical address= base+d=3500+1123=4623
s1
s2
200
5700
6000
700
6700
Physical memory
0
3.4 Segmentation
OS
51
Segment
Limit
Base
1000
0
1500
1000
1
200
5500
2
700
6000
3
2000
3500
s0
1500
Base=
3500
2500
3500
d=
1123
s3
2000
4623
5500
Logical address: <3,1123>
s=3, d=1123
Check if d<limit? 1123<2000, OK
Physical address= base+d=3500+1123=4623
s1
s2
200
5700
6000
700
6700
Physical memory
3.4 Segmentation
52


Segment tables may be implemented in the main
memory or in associative registers, in the same way
it is done for page tables.
Also sharing of segments is applicable as in paging.
Shared segments should be read only and should
be assigned the same segment number.
0
Sharing Segments
OS
53
user1
s0
Editör
s1 Data-1
ST1
seg
lim
base
0
1500
1000
1
2000
3500
1000
Editör
1500
2500
3500
Data-1
2000
5500
Physical memory
0
Sharing Segments
OS
54
user1
Editör
s0
s1 Data-1
user2
s0
Editör
s1 Data-2
ST1
seg
lim
base
0
1500
1000
1
2000
3500
ST2
seg
lim
base
0
1
1500
200
1000
5500
1000
Editör
1500
2500
3500
Data-1
2000
5500
Data-2
Physical memory
200
5700
0
Sharing Segments
OS
55
user1
Editör
s0
s1 Data-1
user2
s0
Editör
s1 Data-2
user3
s0
Editör
ST1
seg
lim
base
0
1500
1000
1
2000
3500
ST2
seg
lim
base
0
1
1500
200
1000
5500
1000
Editör
1500
2500
3500
Data-1
5500
Data-2
ST3
seg
lim
base
0
1500
1000
1
700
6000
2000
Data-3
200
5700
6000
700
6700
s1 Data-3
Physical memory
0
Sharing Segments
OS
56
user1
s0
Editör
s1 Data-1
ST1
seg
lim
base
0
1500
1000
1
2000
3500
s0
Editör
s1 Data-3
Editör
1500
2500
3500
User 2 terminates:
Data-2 removed from
memory, but editör
remains..
user3
1000
Data-1
2000
5500
ST3
seg
lim
base
0
1500
100
1
700
6000
Dat-3
6000
700
6700
Physical memory
0
Sharing Segments
OS
57
1000
User 1 terminates:
Data-1segment is
removed from memory.
Editör
1500
2500
user3
s0
Editör
s1 Data-3
ST3
seg
lim
base
0
1500
100
1
700
6000
Data-3
6000
700
6700
Physical memory
0
Sharing Segments
OS
58
When User 3 terminates:
Data-1
Data-3and
segment
also editor
and
also
segments
editorare
segment
removed
are
removed
from from
memory.
memory.
Physical memory