Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Alessandro Bogliolo

University of Urbino

Nicola Terrassan

and

Davide Bertozzi

University of Ferrara SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Outline 1. Motivation 2. Physical channel design 3. Analytical model

• Design • Validation against HSPICE

4. Macromodel integration in SystemC

• Accuracy assessment

5. Applications and conclusions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Motivation

500M Transistor Platform SPICE-based design space explorations are not viable due to system complexity Design-Productivity Gap Physical gap Hell of nano-scale physics SPI-07 – May 14, 2007 Development of accurate physical models and their abstraction into accurate compact models are mandatory for designing complex circuits • Degradation of RC propagation delay across on-chip interconnects • Low-swing signaling and coding for low-power • Increased sensitivity to on-chip noise sources [email protected]

FF in Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Objective of the work

FF out Driver Receiver RC line

Data out Data in

  Scalability analysis  From 130 to 90 nm, Berkeley Predictive Technology Models  Communication channel  driver, interconnect, receiver, sampling stages  Target: 1 GHz operating frequency, low-power, high throughput links Analytical model   capturing the effects of on-chip noise sources on the channel sub-systems based on the

noise sensitive area concept

Paramet. bit-level model of noisy on-chip communication channels Macromodel integration in SystemC for system-level simulation SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Outline 1. Motivation 2. Physical channel design 3. Analytical model

• Design • Validation against HSPICE

4. Macromodel integration in SystemC

• Accuracy assessment

5. Applications and conclusions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Pseudo-differential interconnect

PDIFF receiver RC Line Driver Static FF Clocked sense amplifier • Makes use of a single wire per bit while still retaining most advantages of differential signaling: low swing, low sensitivity to supply noise • Sources of reliability degradation: mismatches of input pair TNs or REFs SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Delay breakdown

130nm technology node Transistor sizing with Hspice optimization engine Vdd=1.2V, Swing=0.2V

Interconnect length=2mm (intermediate metal layer)   Maximum Frequency: 1.35Ghz

SAFF Flip Flop and PDIFF receiver are the delay bottlenecks SPI-07 – May 14, 2007 [email protected]

• • • • • Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Delay scalability

130 nm technology node 90 nm technology node

Vdd = 1,2 V Swing =

0,2 V

Interconnect length = 2 mm Intermediate metal layer F MAX (130 nm)=

1,35

GHz

• • • • •

Vdd = 1 V Swing =

0,2 V

(to preserve noise margins) Interconnect length = 2 mm Intermediate metal layer F MAX (90 nm)=

1,45

GHz

Propagation delay. Logic 1-to-0 transition

  Scaling of gate delay Interconnect delay does not scale (51% degradation) SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Power breakdown

130nm 90nm 7% 10% 19% 30% 26% SAFF Driver RC line PDIFF Latch NOR 24% 7% 20% 30% Total Power: 98,968 µW 38,532 µW 27%  Scaling factor of power ranges from 0.24x (SAFF) to 0.52x (NOR Latch)     Interconnect power increases by 1.1x

FF, driver and receiver are the most power-hungry components Interconnect power relevant only in 90nm Overall channel power reduces by 60% SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Outline 1. Motivation 2. Physical channel design 3. Analytical model

• Design • Validation against HSPICE

4. Macromodel integration in SystemC

• Accuracy assessment

5. Applications and conclusions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Modelling approach

Data in

splitting the communication channel in two parts: a

driving section

and a

driven section Driving section

FF in Driver

Splitting point Driven section

FF out Receiver RC line

Data out

SPI-07 – May 14, 2007

Provides a signal waveform Poses conditions to its shape to guarantee correct sampling

Error probability evaluated by comparing the signal provided by the driving section with the requirements posed by the driven section [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Noise sensitive areas

Receiver requirements modelled through noise sensitive areas: regions in the signal-time plane which are forbidden to the signal waveform Vin Vin Receiv.

FF clock Vswing=0.2

t0 Hold Time Triggering condition: a requirement on the input voltage at sampling time SA-based receiver imposes holding requirements on the input signal: the stronger the signal the shorter the hold time SPI-07 – May 14, 2007 [email protected]

Vin [V] Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Experimental NSA

nominal

130 nm technology node – 10% positive injected noise on Vdd Thold [ps]  A positive Vdd variation at the receiver shrinks the NSA  The receiver takes less time to sample input signals  Triggering condition reduces to:  Vin higher than 0.140V (for sampling a logic 1)  Vin lower than 0.065V (for sampling a logic 0) SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Parametric NSA model

Measured parameters are manipulated in order to use linear regressions to fit experimental data with a minimum number of fitting coefficients 1  T hold  2  c(V in  V LT ) c  c 1.2

Gnd  c 1.1

Vdd  c 1.0

V LTeff  V LT    V ref  V gnd_ref 2  V ref_nom  V gnd_ref_no m 2   T hold   c 1.2

Gnd  c 1.1

Vdd 1  c 1.0

 V in  V LTeff  SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Model accuracy

• Analytical models of Thold evaluated for different random combinations of noise sources and Vin values • HSPICE sweep simulations conducted with injected noise sources to determine the minimum hold time • Results: – Average error: 3.5% in 130 nm (4.95% in 90nm) – Maximum error: 17.53% in 130 nm (23.5% in 90nm) for concurrent common-mode noise on Vref and Vgnd SPI-07 – May 14, 2007 [email protected]

Data in

FF in Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Driving subcircuit model

Driver RC line

Vin

Far-end signal waveform approximated by a

delay

followed by an

exponential transient

SPI-07 – May 14, 2007 Time (ps) [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels V in V in   Gnd V ref

Exponential transient model

   V ref  Gnd  Gnd V ref    1  1   exp exp   (t (t   t0)c t0)c  

Logic 0 to 1 transition Logic 1 to 0 transition c

is the slope parameter, experimentally approximated by: c   c 2 l 2 1  c 1 l  c 0  V dd V dd_nom

Almost insensitive to Vref variations Depends on interconnect length (l)

Further refined to account for wire parameters: c   c 2 R w R w0   C w C w0  l 2  c 1  ( R R t0 t   C 1 w C w0  R w  C r  R w0  C r0 )  l  R t R t0   C r C r0  c 0  V dd V dd_nom

Rw,Cw: resistance and capacitance per unit length Rt: driver output resistance Cr: receiver input capacitance

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Delay model

We did not derive fitting models of the delay measured from HSPICE simulations, but of those delay values that minimize the MSE of the fitting exponential transients d  c 2  1 (V dd  Gnd)  c 1  R w C w  c 0 Directly proportional to Resistance and Capacitance per unit length Inversely proportional to V dd - Gnd SPI-07 – May 14, 2007 We therefore aim at achieving maximum accuracy in predicting the far-end voltage Vin at sampling time [email protected]

20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Accuracy

Validation against HSPICE for different noise scenarios

Min

MSE for exp. transient

Avg (logic 1) Avg (logic 0) Max 130nm 90nm

In practice, the error on Vin is much smaller than MSE at sampling time

Time (ps) SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Outline 1. Motivation 2. Physical channel design 3. Analytical model

• Design • Validation against HSPICE

4. Macromodel integration in SystemC

• Accuracy assessment

5. Applications and conclusions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Macromodel integration in SystemC

Need: expose the analytical models to a high-level modelling and simulation environment     Interconnect analysis with SPICE accuracy in complex systems Traditional macromodels integrated in VHDL/Verilog SystemC is emerging as the ref. backbone for system-level design C-language programming facilitates HW-SW codesign Analytical macromodel integration in SystemC We exploited the Advanced and Flexible Communication Abstractions in SystemC    Ports:

gateways to communication functions

Interfaces:

declaration of communication functions

Channels:

actual implementation of communication functions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

SystemC communication abstractions

Plug-and-play channels in the link communication model

Interface Interface

HW Module Predefined sc_signal channel (read/write implementation) HW Module Plug-'n'-Play sc_signal with Integrated Analytical model

Output port Input port

SPI-07 – May 14, 2007 Predefined channel augmented with analytical model [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

SystemC vs SPICE accuracy

Accuracy results for 30 different mixes of noise sources

Technology node Sampled logic value Max Error Avg Error Min Error

130nm 1

1,23% 0,46% 0,02%

130nm 0

5,87% 1,76% 0,08%

90nm 1

1,46% 0,38% 0,00%

90nm 0

6,26% 1,48% 0,18%  Average error at sampling time never worse than 2% , max. error less than 7%  Risk of logic value misprediction if sampled voltage close to decision threshold  a

warning

is generated by the SystemC channel  Accounting for Inter-Symbol Interference  Simulation time improvements with SystemC by 10x SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Outline 1. Motivation 2. Physical channel design 3. Analytical model

• Design • Validation against HSPICE

4. Macromodel integration in SystemC

• Accuracy assessment

5. Applications and conclusions

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Communication channel exploration

First application

Injection of noise in the transmitter until a logic error is produced at the receiver

Power supply noise FF TX

Power Supply Noise Type Differential Common Mode SystemC

0,04 0,051

130nm HSPICE

0,048 0,058

Error 0,67% 0,58% SystemC

0,056 0,063

90nm HSPICE

0,063 0,074

Error 0,70% 1,10%

SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Communication channel exploration

Second application: Exploration of different clocking schemes

Native dual clocking schemes with phase shift 1000 ps = 1 GHz Clock TX Clock RX Which is the min. shift for correct sampling at 1 GHz?

SystemC 

35

ps HSPICE 

35

ps (exact matching) SPI-07 – May 14, 2007 [email protected]

Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

Conclusions

 Design of a communication channel for high-performance on-chip links  targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes  low power, low swing signaling  Analytical modelling of channel behavior in presence of noise  Noise sensitive area concept, delay and signal slope models  Macromodel integration into SystemC  Powerful communication abstractions   Plug-and-play backannotated channel Very high accuracy in predicting far-end voltage at sampling time  Average error below 2%, max error below 7%  Improvement of simulation time by 10x  Accounting for Inter-Symbol Interference  Macromodels at work for fast  assessment of channel robustness against noise sources  physical channel design space exploration  Future work: crosstalk analytical macromodelling SPI-07 – May 14, 2007 [email protected]