Transcript Corporate Title – 36pt, Three Lines Max. Anchor: Bottom Left

Industry Pulse:
Trends in Functional Verification
Harry Foster
Chief Scientist Verification
Design Verification Technology
MemoCODE 2013
Extrapolating From Current Conditions
Disregards Future Innovation
“In 1910, in the early history telephony, a Bell telephone statistician
projected a massive ramp-up in switchboard operator jobs as telephone
use grew, until “every woman in America” would be required.”
Source: Future Savvy: Identifying trends to Make Better Decisions, Manage Uncertainty, and Profit From Change Adam Gordon, 2008
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Functional Verification Market
According to EDAC
38% Growth Between 2010 2012
965
Millions ($)
1000
800
700
600
400
200
0
2010
2012
EDAC: Market Statistics Service 2007 Annual Summary Report
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Functional Verification Market
According to EDAC
Simulation 13% Growth
Emulation 94% Growth
Formal 31% Growth
Millions ($)
430
400
380
365
300
200
170
190
130
100
0
2010
2012
EDAC: Market Statistics Service 2007 Annual Summary Report
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2012 Wilson Research Group
Functional Verification Study

Conducted by Wilson Research Group
— Commissioned by Mentor Graphics
— Format followed 2002, 2004 Collett studies for trend analysis, as
well as the 2007 FarWest Research Study

Worldwide study
— Overall confidence of 95% plus/minus 4.05%

This was a blind study!
— To eliminate any bias in the results

This was a balanced study!
Wilson Research Group
— No single vendor dominated responses
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Who Participated In The Survey
Participant’s market segment
60%
Non-FPGA 2012
50%
Study Participants
FPGA 2012
40%
30%
20%
10%
0%
ASIC Vendor
Fabless IC
Vendor
IC
Manufacturer
Systems
Company
Design
Services
Company
IP Vendor
Company
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Other
Who Participated In The Survey
Participant’s job title
60%
Non-FPGA 2012
Study Participants
50%
FPGA 2012
40%
30%
20%
10%
0%
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Overview

Beyond Theory

Beyond Standards

Beyond the Status Quo
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Beyond Theory in Terms of Rising Complexity
BEYOND THEORY
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Difference Between Theory and Practice
In theory there is no difference between
theory and practice, but in practice there is.
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Difference Between Theory and Practice
Theory: Everything is clear, but nothing works.
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Difference Between Theory and Practice
Practice: Everything works, but nothing is clear.
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Difference Between Theory and Practice
The problem is sometimes theory meets practice:
Nothing works and nothing is clear.
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Beyond Theory in Terms of Rising Complexity

What does this really mean?

What makes things complex?

How do we measure complexity?
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What Makes Something Complex?

System consisting of many interconnected parts
— Examining the individual parts tells you nothing about the system

Complex does not necessarily mean complicated
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Designs are Getting More Complex
40%
Study Participants
35%
30%
2007: Mean 90nm
2010: Mean 65nm
2012: Mean 45nm
2007
2010
2012
25%
20%
15%
10%
5%
0%
Process Geometry
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Designs are Getting More Complex
Number of gates of logic and datapath, excluding memories
30%
Non-FPGA Study Participants
25%
About a 1/3rd of designs below 5M gates
About a 1/3rd of design between 5M - 20M gates
About a 1/3rd of designs great than 20M gates
20%
2002
15%
2007
2010
10%
2012
5%
0%
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Designs are Getting More Complex
Mean number of gates of logic and datapath, excluding memories trends
Non-FPGA Mean Design Size Gates (M)
12
11,1
10
8
6,1
6
4
2,7
2
0,4
0
2002
2007
2010
2012
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Designs are Getting More Complex
79% of designs contain one or more embedded processors
60%
Non-FPGA Study Participants
50%
2004
40%
2007
2010
2012
30%
20%
28%
22%
21%
10%
10%
13%
6%
0%
NONE
1
2
3
4
5 or MORE
Number of Embedded Processors for Non-FPGA Designs
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Designs are Getting More Complex
Non-FPGA Mean number
of Embedded Processors
3
Mean
number of embedded processors continues to rise
2,25
1,96
2
1,46
1,06
1
0
2004
2007
2010
2012
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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FPGAs are Getting Complex Too!
56% of FPGAs contain one or more embedded processors
44%
Survey Participants
40%
38%
FPGA
30%
20%
Non-FPGA
28%
22%
21%
10%
11%
10%
6%
4%
1%
0%
NONE
1
2
13%
2%
3
4
5 or MORE
Number of embedded processors
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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How do we measure complexity?

Computational complexity theory used in computer science
Operations
O(1)
O(logn)
O(n)
O(nlogn)
O(n^2)
O(2^n)
O(n!)
Elements

There are no generally accepted metrics!
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Is bug density a good proxy?
Channel
Encoder
TX
Decoder
Compressed
Audio

Single, sequential data
streams
—
—
—
—
—
Floating point unit
Graphics shading unit
DSP convolution unit
MPEG decode
...
Sequential data streams
1x number of bugs
HF, MemoCODE, 2013
PHY
RX

Multiple, concurrent data
streams
—
—
—
—
—
Cross bar
Bus traffic controller
DMA controller
Standard I/F (e.g., PCIe)
...
Concurrent data streams
5x number of bugs
-Ted Scardamalia, internal IBM study
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Data Link Layer
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Concurrency is Complicated to Verify
Packet-Based Design
From
Fabric
Tx
Transaction
Layer Packet
Reformater
Retry Buffer
To
PHY
Arbiter
Data Link
Layer Packet
Reformater
Rx
From Rx
Channel
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Expensive
Prohibitive
Critical
Threshold
Affordable
Cost/Effort
Maybe effort is a good proxy?
Complexity
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Verification Consumes Majority of Project Time
Total Project Time Spent in Verification
Non-FPGA Study Participants
25%
2007: Mean 49%
2010: Mean 56%
2012: Mean 56%
20%
2007
2010
2012
15%
10%
5%
0%
1%-20%
21%-30%
31%-40%
41%-50%
51%-60%
61%-70%
71%-80%
>80%
Time (Percent)
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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More and More Verification Engineers
Mean peak number of design vs. verification engineers
~ 1-to-1 ratio
of peak design
and verification
engineers
11%
58%
8,4
Verification
Engineers
7,8
8,1
8,5
Design
Engineers
2007
2010
2012
7,6
4,8
4%
5%
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Where Verification Engineers Spend Their Time
More time spent in debug
than any other task!
36%
4%
Test Planning
Testbench Development
16%
23%
22%
Creating and Running Test
Debug
Other
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Designers Doing More and More Verification
Design Engineer Project Time
2007 - 2012
54%
53%
47%
46%
2007
2012
Doing Design
2007
2012
Doing Verification
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Time Designers Spends in Design vs. Verification
At this rate…
In 25 years, ALL
of a designer’s
time will be
devoted to
verification
100
Time (Percent)
80
60
Time Design Engineers
Spends Doing:
40
Design
20
Verification
0
2007
2012
2017
2022
2027
2032
2037
Project Time 2007 - 2037
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Design Reuse Trends
41%
2007
Non-FPGA Study Participants
40%
33%
30%
35%
2012
28%
22%
20%
13%
13%
15%
10%
0%
NEW LOGIC
REUSED LOGIC
(Developed in-house)
PURCHASED IP
ANALOG, RF AND/OR
MIXED SIGNAL
Design Composition
Source: Wilson Research Group and Mentor Graphics.
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Verification Reuse
Mean testbench composition trends
Non-FPGA Study Participants
50%
40%
50%
39%
41%
2007
44%
2012
30%
20%
17%
8%
10%
0%
NEW
REUSED FROM OTHER
DESIGNS
ACQUIRED EXTERNALLY
Testbench Composition
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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With All This Effort, How are We Doing?
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Project’s Schedule Completion Trends
35%
2007: 67% behind schedule
2010: 66% behind schedule
2012: 67% behind schedule
Study Participants
30%
25%
2007
20%
2010
2012
15%
10%
5%
0%
More than 10%
EARLY
ON-SCHEDULE
Ahead of schedule
20%
40%
>50% BEHIND
SCHEDULE
Behind Schedule
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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FPGA vs. Non-FPGA Completion Trends
35%
30%
Non-FPGA: 67% behind schedule
FPGA: 67% behind schedule
Study Participants
25%
20%
Non-FPGA
FPGA
15%
10%
5%
0%
More than 10%
ON-SCHEDULE
20%
40%
>50% BEHIND
EARLY
SCHEDULE
Non-FPGA vs. FPGA completion compared to project's original schedule
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Required Number of Spins
Non-FPGA Study Participants
50%
40%
2004
2007
30%
2010
2012
20%
10%
0%
1
FIRST
SILICON
SUCCESS
2
3
4
5
6
Number of Required Spins
7
SPINS or
MORE
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Types of Flaws
Non-FPGA Study Participants
60%
50%
2004
40%
2007
2010
30%
2012
20%
10%
0%
Trends in Types of Flaws Resulting in Respins
* Multiple answers possible
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Root Cause of Functional Flaws
Non-FPGA Study Participants
90%
80%
2002
70%
2004
2007
60%
2010
50%
2012
40%
30%
20%
10%
0%
DESIGN ERROR
CHANGES IN
INCORRECT or
FLAW IN
SPECIFICATION INCOMPLETE
INTERNAL
SPECIFICATION REUSED BLOCK,
CELL, MEGACELL
or IP
FLAW IN
EXTERNAL IP
BLOCK or
TESTBENCH
OTHER
Root Cause of Functional Flaws
* Multiple answers possible
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Cost of Find Functional Flaws
uct
ion
rod
Vo
l um
eP
Design Cycle
Sa
mp
li ng
Si l
ico
n
Ea
rl y
el e
as
e
Ta
pe
R
La
you
t
De
sig
nR
In i
tia
l
evi
ew
$10,000,000
$1,000,000
$100,000
$10,000
$1,000
$100
$10
$1
De
sig
n
Cost To Fix
Relative Cost Of Finding Bugs
Silicon Debug, Doug Josephson and Bob Gottlieb, (Paul Ryan)
D. Gizopoulos (ed.), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006
© 2010
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Company
Confidential
Confidential
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Beyond arguing over who won the standards war
BEYOND STANDARDS
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Standardization of Languages
Non-FPGA Study Participants
80%
SystemVerilog grew 8.3% between 2010 and 2012
2007
60%
2010
2012
40%
20%
0%
VHDL
Verilog
Synopsys Vera
System C
SystemVerilog Specman e
C/C++
Languages Used for Verification (testbenches)
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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OTHER
Testbench
SystemVerilog Adoption by Design Size
100%
Non-FPGA Study Participants
89%
80%
60%
71%
58,8%
40%
20%
0%
< 5M
5 - 20M
> 20M
SystemVerilog Adoption by Design Size
(Gate Count Excluding Memories)
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Standardization in Base Class Libraries
486% UVM growth between 2010 and 2012
46% UVM projected growth in the next twelve months
Non-FPGA Study Participants
40%
2010
2012
30%
20%
10%
0%
Accellera
UVM
OVM
Mentor
AVM
Synopsys Synopsys Cadence
VMM
RVM
eRM
Cadence
URM
Other
Testbench Methodologies and Base-Class Libraries
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Standardization of the SoC Verification Process

Ten years ago, IC/ASIC verification was partitioned into
two main steps:
Block
Block-Level
Verification
Full Chip
Integration
Verification
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Standardization of the SoC Verification Process

Emerging from ad hoc to systematic processes
IP
Block-Level
Verification
Subsystem
Interconnect
Verification
SoC
Integration
Verification
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System
Application
/ SW
Verification
Company Confidential
Beyond surviving by maintaining the status quo
BEYOND THE STATUS QUO
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The Verification Paradox

A good verification process lets you get the most out of
best-in-class verification tools
Start
Tools
Ad Hoc
Processes
6-9%
Cost Increase
Start
Process
Tools
20-30%
Cost Savings
Source: Cisco Momentum Research Group
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Standardization of the SoC Verification Process
Block-Level
Verification
Interconnect
Verification
Integration
Verification
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Application
/ SW
Verification
Company Confidential
Use of Advanced Verification Techniques
2007
2012
48%
Code coverage
70%
37%
Assertions
68%
40%
Functional coverage
71%
41%
Constrained-Random Simulation
62%
0%
20%
40%
60%
Non-FPGA Study Participants
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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80%
Directed vs Constrained-Random Simulation
100%
Non-FPGA Study Participants
80%
56%
49%
60%
Directed
Constrined-Random
40%
20%
44%
51%
0%
2010
2012
Mean Directed vs. Constrained-Random Simulation Trends
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Larger Designs Use More Formal
41%
Non-FPGA Study Participants
40%
30%
20%
26%
20%
10%
0%
< 5M
5 - 20M
> 20M
Formal Property Checking Adoption by Design Size
(Gate Count Excluding Memories)
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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The Evolution of Formal Technology
High
Effort
Formal
Property
Checking
Automated
Applications
Fully
Automatic
Formal
Low
Effort
1990s
2000s
Today
Formal
Experts
Everyone
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Standardization of the SoC Verification Process
Block-Level
Verification
Interconnect
Verification
A57
A57
A57
Integration
Verification
A57
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Application
/ SW
Verification
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Standardization of the SoC Verification Process
Block-Level
Verification
Interconnect
Verification
Integration
Verification
Application
/ SW
Verification
IP Blocks connectivity
— Access all memories
— Access all registers, such as control
— Configurations work
— Functional scenarios and use-cases
— Verify multiple clock domain crossings
—
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Mean Number of Clock Domains by Design Size
Mean Number of Clock Domains
14
11,48
12
9,36
10
8
6
5,21
4
2
0
< 5M
5 - 20M
> 20M
Mean Number of Clock Domains by Design Size
(Gates Excluding Memories)
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Standardization of the SoC Verification Process
Block-Level
Verification
Interconnect
Verification
Integration
Verification
Application
/ SW
Verification
Boot OS
— Load System Drivers
— Run Application SW
—
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SoC Design & Verification Involves Lots of SW
$100
It’s the software, stupid! -Gary Smith
($ M)
$80
$60
$40
$20
$0
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
Total SW Engineering Costs + ESA Tool Costs
Total HW Engineering Costs + EDA Tool Costs
Source: ITRS 2010, Impact of Design Technology on SoC Consumer Portable Implementation Cost
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2012
As Design Sizes Increase…Emulation Up,
FPGA Prototyping Down in 2012
60%
57%
50%
Non-FPGA Study Participants
< 5M
5 - 20M
> 20M
50%
45%
40%
32%
30%
28%
20%
18%
10%
0%
HW Acceleration/Emulation
FPGA Prototyping
Adoption by design size for those doing
HW acceleration/emulation and FPGA Prototyping
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
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Integrated Simulation/Emulation/Software
Verification Environments Emerge
Design under Test
Testbench
Acceleration
System Level
OVM/UVM
SystemC/C++
Virtual Prototype
Monitors
SW Debug
Processor Debug
Assertions &
Checkers
JTAG
Protocol Solutions
Protocol Solutions
Virtual Devices &
Transactors
Physical Devices
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Coverage and Power
Across all aspects of verification
Block
Block-Level
Verification
Subsystem
Interconnect
Verification
SoC
Integration
Verification
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System
Application
/ SW
Verification
Company Confidential
The Rising Importance of Coverage
Signoff criteria trends
WHEN ALL TESTS DOCUMENTED IN THE
VERIFICATION PLAN ARE COMPLETE AND PASS
WHEN THE PROJECT PLAN SAYS SIGN-OFF,
ASSUMING VERIFICATION LOOKS OK
WHEN COVERAGE SAYS WE HAVE ACHIEVED A
TARGET
WHEN THE EMULATED OR PROTOTYPED DESIGN IS
WORKING IN-SITU
WHEN THE RATE OF BUGS FOUND PER WEEK DROPS
BELOW A SPECIFIED GOAL
WHEN WE CAN NO-LONGER THINK OF ANY MORE
TESTS TO WRITE
2007
2012
WHEN THE PROJECT PLAN SAYS SIGN-OFF,
REGARDLESS OF STATUS
OTHER
0%
10%
20%
30%
40%
Non-FPGA Study Participants
* Multiple answers possible
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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50%
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Unified Coverage Interoperability Standard
New Accellera UCIS Standard Announced at DAC 2012
Formal
Simulation
Emulation
UCIS API
Coverage
Database
Analysis
Testplan
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Trends in Power Management Verification
Hypervisor/OS control of power
management
67% of the industry actively
manages power
Application-level power management
Operation in each system power state
Interactions between power domains
Hardware power control
sequence generation
Transitions between system
power states
Power domain state
reset/restoration
Power domain power
down/power up
0%
20%
40%
60%
80%
Aspects of Non-FPGA Power Managed Design That Are Verified
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Power Trends
35%
About 10% of power managed designs
perform no power-aware simulation!
Non-FPGA Study Participants
30%
25%
20%
15%
10%
5%
0%
Percentage of total simulations that were power-aware
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
© 2013 Mentor Graphics Corp.
HF - January 2013 Master Set, WRG & MG Study Results
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Power Trends
35%
Median Verification Resources: 20% -29%
Non-FPGA Study Participants
30%
25%
20%
15%
10%
5%
0%
Percentate of Verification Resources Focused on Power
Management
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
© 2013 Mentor Graphics Corp.
HF - January 2013 Master Set, WRG & MG Study Results
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Power Trends
Notation used to describe power intent
27%
24%
Non-FPGA Study Participants
25%
22%
20%
15%
15%
10%
6%
6%
5%
0%
* Multiple answers possible
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission
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Beyond the Status Quo
Standardization of the SoC Verification Process
IP
Block-Level
Verification
Subsystem
Interconnect
Verification
SoC
Integration
Verification
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System
Application
/ SW
Verification
Company Confidential
The Productivity Gap
BACK TO THE FUTURE
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Design Productivity Gap
Capacity
Silicon
Density
Design
Productivity
Time
Source: SEMATECH
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Verification Productivity Gap
Capacity
Silicon
Density
Design
Productivity
Verification
Productivity
Source: SEMATECH
Time
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Closing The Verification Gap
Reuse
Acceleration
?
Abstraction
Methodology
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Managing Complexity
#include "systemc.h"
SC_MODULE(adder) // module
(class) declaration {
sc_in<int> a, b; // ports
sc_out<int> sum; void
do_add() // process { sum =
a + b; } SC_CTOR(adder) //
constructor {
SC_METHOD(do_add); //
register do_add to kernel
sensitive << a << b; //
sensitivity list of do_add } };
100s of lines
of TLM
Millions of
Lines of RTL
100s of Millions of Gates
Billions of Transistors
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Productivity Gains Through Abstraction
Simulation
Function
arguments
C/C++
Transaction
Untimed TLM
Transaction
Timed TLM
10,000x (1 min)
1,000x
100x
clk
Cycle Accurate
Protocol
clk
Protocol
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RTL
10x
1x (7 days)
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Bug Prevention vs. Bug Hunting
What’s the advantage of SystemC compared with RTL?
There are two different aspects – quality and time schedule.
Today, a full chip on SystemC will run around 10 MHz, and
you will never reach that speed using RTL or a lower-level
abstraction. It’s similar to a prototype speedup. Previously
with RTL designs, our bug rate was in the range of 10 to 50
bugs per square millimeter. Now we are at less than one bug
per millimeter squared. So we have both quality and speed
of development.
Source: EETimes, 2007, Laurent Ducousso, who manages intellectual-property (IP) verification for
STMicroelectronics’ Home Entertainment Division
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Summary

Beyond theory in terms of rising complexity

Beyond arguing over who won the standards wars

Beyond surviving by maintaining the status quo
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© 2013 Mentor Graphics Corp.
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Company Confidential