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Wireless IC Node with Compression Heuristics (W.I.N.C.H.) Final Design Review Steve Jocke, Kyle Ringgenberg, Stuart Wooters <scj4s, kringg, wooters>@virginia.edu System Data Flow Overview E cycle avg PIC Overview • PIC16C5X.UVa Stats – 4 Interrupts / 3 Input ports / 5 output ports / 32 Instruction – Operating voltage of 300mV – Input clock frequency of 800KHz • Clock divided down to 200Khz for PIC internal cycles • Approximately 200 Instructions (I-cycles) between ADC Samples • System overhead requires approximately 30 I-cycles – Required to track input values for gain adjustment to ADC – Leaves ~ 170 I-Cycles free for compression, second core not required Run Length Encoding • Replace Repetition with Occurrence Counts – Lossless: Only Identical Values Replaced • 0 0 0 1 3 5 5 6 [3]0 1 3 [2]5 6 – Lossey: Values with a Tolerance Replaced • 0 0 0 1 3 5 5 6 [4]0 3 [3]5 – Variable Parameters • Codeword Size – Max Repetition Length • Block Size – Insert Repetition Code Every Block – CODE x BLOCK = WORD • Tolerance – “Stray-ability” Run Length Encoding Run Length Encoding Run Length Encoding • All Variants Require Additional Repetition Blocks • Compression Ratio – Lossless • Poor – Worst Case is Worse than Raw – Lossey • Excellent – Saturates to Best Compression Ratio • Executable in O(n) – 36 Clock Cycles – 7 Registers Delta Encoding • Replace Values with Changes in Values – Lossless Global: Greatest Δ Dictates Remapping • 0 0 0 1 3 5 5 6 8x 3-bit “Words” 24 bits • 0 0 1 2 2 2 1 7x 2-bit “Words” 14 bits – Lossless Local: Each Δ Treated Independently • 0 0 1 2 2 2 1 4x 1-bit, 3x 2-bit “Word” 10 bits • Additional Data for “Word” Lengths – Lossey Global: Mean Δ Dictates Remapping • 0 0 1 2 2 2 1 8x 1-bit 8 bits • Decoded as: 0 0 0 1 2 3 4 5 Delta Encoding Tightly Clustered Long Tail Delta Encoding Longer Tail, but no Bit Change! Delta Encoding 3 2.5 2 Raw deltaG deltaG' deltaL 1.5 1 0.5 0 ecg1 ecg2 ecg3 Delta Encoding • All Variants Require Additional Sign Bit • Compression Ratio – Lossless • Mediocre – Significant Degree of Overhead Bits – Lossey • Mediocre – Fidelity is Data Dependent • Execution in O(n) – 37 Clock Cycles – 6 Registers Compression Conclusions 14 12 10 8 10x Raw Lossless Lossey 6 4 2 0 ecg1 ecg2 ecg3 Mixer Design Vdd 1.2V • Active Power: – 50GHz LO – 100Mbs – 9.23mW • Active Power: – 1.5 GHz LO – 100Mbps – 716.67uW 15GHz Local Oscillator • Startup Delay: – 101.626ps • Startup Power: – 4.471mW • Run Power: – 6.050mW • Off Power: – 69.3914μW LO – 3 Stage Inverter and Buffer 1.5 GHz • Startup Time: – 2.3ns • Startup Energy: – 6.92pJ • Startup Power: – 3mW • Avg Power: – 3.502mW • Off Power: – 1.804μW High Speed Power Examples • • • • • VCO Core: 1mW1 51GHz Mixer:97mW2 9-50GHz Gilbert Cell Amplifier 54mW3 60GHz 1.52nJ/bit (100Mbps) 3.04μJ/2Kbit (100Mbps) 1. Tiebout, M.; Wohlmuth, H.-D.; Simburger, W., "A 1V 51GHz fully-integrated VCO in 0.12/spl mu/m CMOS," Solid-State Circuits Conference , 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , vol.2, no., pp.238-239, 2002 2. Lin, C.-S.; Wu, P.-S.; Chang, H.-Y.; Wang, H., "A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology," Microwave and Wireless Components Letters, IEEE , vol.16, no.5, pp. 293-295, May 2006 3. Doan, C.H.; Emami, S.; Niknejad, A.M.; Brodersen, R.W., "Millimeter-wave CMOS design," Solid-State Circuits, IEEE Journal of , vol.40, no.1, pp. 144-155, Jan. 2005 Power Consumption of PIC (No Compression) Time μ sec Power Consumption of PIC (cont’d) • Measurements – • PIC Power Summary – – – • Ultrasim Simulator used to measure current • Set in MS (Mixed Signal / Analog Mode) Without compression • 1.) NOP Inst Power 318.1nW (Averaged over 4 NOP’s) • 2.) AVG Inst Power 322.95nW (All runtime - 2mS) With compression • 3.) AVG Inst Power 336.78nW (Over Compression Algorithm) • 4.) AVG Inst Power 324.46nW (all runtime – 2mS) Final Stats • Overall Inst Power 323.7nW • Delta Power Modes 1.51nW Conclusion – Power Consumption is about the same no matter what operation • Using free I-cycles recovers wasted power • Also could throttle back clock frequency Energy Totals for Communication Channel • 15GHz – On Energy (Mixer + LO): • 152.8pJ/bit • 305.6nJ/2Kbit – Off Power (LO): • 69.39μW • 1.5GHz – On Energy (Mixer + LO): • 35.06pJ/bit • 70.1nJ/2Kbit – Off Power (LO): • 1.804μW 4. Roving Networks RN-41 V1.5 11/14/07 Documentation • Bluetooth4 – On Energy: • 297.5pJ/bit – 165nJ/bit – Sleep Power • 825μW – Idle Power • 8.25mW Summary • Base Case (Bluetooth) • Compression (10/1) – .324nJ/Sample (PIC) – 2.38nJ/byte (Bluetooth) – 827nJ/Sample • No Compression – .324nJ/Sample (PIC) – 2.38nJ/byte (Bluetooth) – 842.4nJ/Sample • Wireless • Compression (10/1) – .324nJ/Sample (PIC) – 1.224nJ/byte (LO) – 74.5nJ/Sample • No Compression – .324nJ/Sample (PIC) – 1.224nJ/byte (LO) – 68.8μJ/Sample