Transcript Document

Concepts of System Design

The example used here is a Bit-pattern associative router.
It has components that include:
Input and Output Ports
 Routing and Arbitration module
 The Switch as well as local node circuitry

The idea is to understand what the system requirements
are and what each component’s fuction is.
 In this case we design just the routing and arbitration unit


Its function is to get the message header and determine the
appropriate route the message must follow to reach its
destination.
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Router Architecture
local node
input
ports
switch
output
ports
routing & arbitration
2
Associative router scheme
destination address
Selection function
routing
function
priority
output port
port assignment
3
General routing function
destination address
c2
c1
c0
this node
x
x
c0
x port
x
c1
c0
y port
c2
c1
c0
z port
4
Routing function
 IF
cond THEN assign(out_put)
 Cond
=
5
Case statement
 IF
cond1 THEN assign(out_port1)
 ELSE IF cond2 THEN assign(out_port2)
 ELSE IF cond3 THEN assign(out_port3)
.
.
.
 ELSE IF condN THEN assign(out_portN)
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Router organization
Normal operation
destination address
to switching network
(from input port)
(output port)
Refresh (DCAM)
no match
Port
Assignment
(DRAM)
row select
Bit-Pattern
Associative
Unit
(DCAM)
(SF)
Port assignment Register
selection function
row select
Search argument register
Refresh (DRAM)
The Blue Rows indicate matching words/addresses and
Only one is selected and routed
7
Programming mode
Program Data
Program Data
row select
Bit-Pattern
Refresh (DCAM)
(DCAM)
Input Latch
(SF)
Input Latch
selection function
Search argument register
(Output Port Assignment)
no match
Port assignment Register
row select
(Current Address)
Refresh (DRAM)
The row select, selects a word to write to and the action is the
same for both the Dynamic Content Addressable Memory
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(CAM) and the Dynamic RAM (DRAM)
Basic element of the bit-pattern
associative unit
One of many flavors
Of dynamic CAM
Bit
Bit
write
sb1
sb0
read
Match line
Evaluate
9
Tenary digit stored in the DCAM cell
Sb1
Sb0
state
0
0
X(don’t care)
0
1
1(one)
1
0
0(zero)
1
1
Not allowed
10
Basic cell of the selection function
w/o priority lookahead
11
4-bit encoder w/o lookahead
12
Basic cell of the selection function
with priority lookahead
13
4-bit priority lookahead encoder
14
The Refresh Basic Cell

DCAM Refresh
Bit
Bit
read
read

Good For DRAM too
VDD
VDD
write
write
C2MOS Refresh Register
15
Timing Operation
 Match
Operation Timing Sequence
F1
Two phase clocking
T21
Get
input 1
F2
T12
Latch & pass input
1 to bit lines
Get
input 2
Compare 1 input to Write data back
Read &
stored data. Evaluate after refreshing
refresh
matchline @ T21 & F2 (@ T21 & F1
data
Reset DRAM Precharge
Get
priority Select priority
Match
encoder ignored
line
Precharge
DRAM
bitlines
Reset
priority
encoder
Precharge
DRAM
bitlines
Latch & pass input
2 to bit lines
Get
input 3
Latch & pass input
2 to bit lines
Get
input 4
Compare 2 input to
Compare 3 input to Write data back
Precharge Read &
stored data. Evaluate
stored data. Evaluate after refreshing
bitlines refresh
matchline @ T21 & F2
matchline @ T21 & F2 (@ T21 & F1
data
Select
DRAM
Precharge
Get
priority
Match
line
Read data 1 from selected
row, latch data. @ F2 send
data out
Reset
priority
encoder
Select
DRAM
Precharge
Get
priority
Match
line
Input Latch operation
Matching Unit (DCAM)
operation (timing events)
Reset
priority Priority Encoder operation
encoder (timing events)
Precharge Read data 2 from selected Precharge
DRAM row, latch data. @ F2 send DRAM
bitlines data out
bitlines
Output port activity
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