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MIPS Microarchitecture Pipeline Hazards and Stalls Lecture 22 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007 1 Basic Pipelined Processor CLK RegWriteD Control MemtoRegD Unit 31:26 5:0 PC' PCF 1 A RD Instruction Memory RegWriteM RegWriteW MemtoRegW MemtoRegE MemtoRegM MemWriteD MemWriteE MemWriteM BranchD BranchE BranchM Op ALUControlD ALUControlE2:0 Funct ALUSrcD ALUSrcE RegDstD RegDstE ALUOutW CLK InstrD 25:21 20:16 A1 A2 A3 WD3 CLK WE3 RD2 0 SrcBE 1 Register File RtE RdE 0 15:0 PCPlus4F Sign Extend PCPlus4D ALUOutM WriteDataE WriteDataM WriteRegE4:0 WriteRegM4:0 A RD Data Memory WD 0 ReadDataW 1 WriteRegW 4:0 1 + 15:11 WE ZeroM SrcAE RD1 20:16 4 PCSrcM SignImmE <<2 + 0 CLK RegWriteE ALU CLK CLK CLK PCBranchM PCPlus4E ResultW 2 Pipeline Hazard 1 2 3 4 5 6 7 8 Time (cycles) add $s0, $s2, $s3 and $t0, $s0, $s1 or $t1, $s4, $s0 sub $t2, $s0, $s5 IM add $s2 RF $s3 IM and DM + $s0 RF $s1 IM or RF DM & $s4 RF $s0 IM $s0 sub | $s0 RF $s5 $t0 RF DM - $t1 RF DM $t2 RF 3 Data Forwarding 1 2 3 4 5 6 7 8 Time (cycles) add $s0, $s2, $s3 and $t0, $s0, $s1 or $t1, $s4, $s0 sub $t2, $s0, $s5 IM add $s2 RF $s3 IM and DM + $s0 RF $s1 IM or RF DM & $s4 RF $s0 IM $s0 sub $t0 RF DM | $t1 RF $s0 RF $s5 - DM $t2 RF 4 Data Forwarding CLK Control Unit 31:26 5:0 A RD Instruction Memory RegWriteM RegWriteW MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM ALUControlD2:0 ALUControlE2:0 Op ALUSrcD ALUSrcE Funct RegDstD RegDstE BranchD BranchE InstrD CLK WE3 25:21 A1 20:16 A2 RD2 A3 Register WD3 File RD1 25:21 20:16 15:11 15:0 4 PCSrcM BranchM Sign Extend SrcAE 00 01 10 00 01 10 RsD RsE RtD RtE RdE RdE WE ZeroM 0 SrcBE 1 ALUOutM WriteDataM WriteDataE A RD Data Memory WD ReadDataW ALUOutW 0 1 WriteRegE4:0 SignImmD WriteRegM4:0 1 0 WriteRegW 4:0 SignImmE + <<2 PCPlus4D PCPlus4E PCBranchM RegWriteW ResultW RegWriteM PCPlus4F ForwardBE PCF RegWriteE MemtoRegD ForwardAE PC' RegWriteD CLK + 0 1 CLK ALU CLK CLK CLK Hazard Unit 5 Stalling 1 2 3 4 5 6 7 8 Time (cycles) lw $s0, 40($0) IM lw $0 RF 40 DM + $s0 RF Trouble! and $t0, $s0, $s1 or $t1, $s4, $s0 sub $t2, $s0, $s5 IM and $s0 RF $s1 IM or DM & $s4 RF $s0 IM sub $t0 RF DM | $t1 RF $s0 RF $s5 - DM $t2 RF 6 Stalling 1 2 3 4 5 6 7 8 9 Time (cycles) lw $s0, 40($0) and $t0, $s0, $s1 or $t1, $s4, $s0 IM lw $0 RF 40 IM and DM + $s0 RF $s1 IM or $s0 RF $s1 IM or $s0 RF DM & $s4 RF $s0 Stall sub $t2, $s0, $s5 IM sub | $s0 RF $s5 $t0 RF DM - $t1 RF DM $t2 RF 7 Stalling Hardware CLK Control Unit 31:26 5:0 PC' PCF EN A Instruction Memory RegWriteE RegWriteM RegWriteW MemtoRegD MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM ALUControlD2:0 ALUControlE2:0 Op ALUSrcD ALUSrcE Funct RegDstD RegDstE BranchD BranchE CLK WE3 25:21 A1 20:16 A2 RD2 A3 Register WD3 File RD1 20:16 + 15:11 15:0 4 PCSrcM BranchM CLK InstrD RD RegWriteD 25:21 Sign Extend SrcAE 00 01 10 00 01 10 0 SrcBE 1 RsE RtD RtE RdE RdE ALUOutM WriteDataM WriteDataE RsD WE ZeroM A RD Data Memory WD ReadDataW ALUOutW 0 1 WriteRegE4:0 SignImmD WriteRegM4:0 1 0 WriteRegW 4:0 SignImmE + <<2 PCPlus4D PCPlus4E CLR EN PCPlus4F PCBranchM RegWriteW RegWriteM MemtoRegE ForwardBE ForwardAE FlushE StallD ResultW StallF 0 1 CLK ALU CLK CLK CLK Hazard Unit 8 Control Hazards CLK Control Unit 31:26 5:0 PC' PCF EN A Instruction Memory RegWriteE RegWriteM RegWriteW MemtoRegD MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM ALUControlD2:0 ALUControlE2:0 Op ALUSrcD ALUSrcE Funct RegDstD RegDstE BranchD BranchE CLK WE3 25:21 A1 20:16 A2 RD2 A3 Register WD3 File RD1 20:16 + 15:11 15:0 4 PCSrcM BranchM CLK InstrD RD RegWriteD 25:21 Sign Extend SrcAE 00 01 10 00 01 10 0 SrcBE 1 RsE RtD RtE RdE RdE ALUOutM WriteDataM WriteDataE RsD WE ZeroM A RD Data Memory WD ReadDataW ALUOutW 0 1 WriteRegE4:0 SignImmD WriteRegM4:0 1 0 WriteRegW 4:0 SignImmE + <<2 PCPlus4D PCPlus4E CLR EN PCPlus4F PCBranchM RegWriteW RegWriteM MemtoRegE ForwardBE ForwardAE FlushE StallD ResultW StallF 0 1 CLK ALU CLK CLK CLK Hazard Unit 9 Control Hazards 7 6 5 4 3 2 1 9 8 Time (cycles) 20 beq $t1, $t2, 40 24 and $t0, $s0, $s1 $t1, $s4, $s0 28 or 2C sub $t2, $s0, $s5 30 ... IM lw $t1 RF $t2 IM and DM - $s0 RF $s1 IM or RF DM & RF $s0 IM sub DM | $s0 RF $s5 IM slt - $s2 RF $s3 RF DM slt slt $t3, $s2, $s3 Flush these instructions $s4 ... 64 RF RF DM $t3 RF 10 Control Hazards CLK Control Unit 31:26 5:0 CLK CLK RegWriteD RegWriteE RegWriteM RegWriteW MemtoRegD MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM ALUControlD2:0 ALUControlE2:0 Op ALUSrcD ALUSrcE Funct RegDstD RegDstE BranchD PC' PCF EN A InstrD RD Instruction Memory WE3 25:21 A1 20:16 A2 RD2 A3 Register WD3 File RD1 20:16 + 15:11 15:0 4 Sign Extend CLK = 25:21 WE SrcAE 00 01 10 00 01 10 0 SrcBE 1 WriteDataE RsD RsE RtD RtE RdE RdE ALUOutM WriteDataM A RD Data Memory WD ReadDataW ALUOutW 0 1 WriteRegE4:0 SignImmD WriteRegM4:0 1 0 WriteRegW 4:0 SignImmE + <<2 PCPlus4D CLR CLR EN PCPlus4F PCBranchD RegWriteW RegWriteM MemtoRegE ForwardBE ForwardAE FlushE StallD ResultW StallF 0 1 PCSrcD EqualD CLK ALU CLK CLK Hazard Unit 11 Control Hazards 1 2 3 4 5 6 7 8 9 Time (cycles) 20 beq $t1, $t2, 40 24 and $t0, $s0, $s1 28 or 2C sub $t2, $s0, $s5 30 ... IM lw $t1 RF $t2 IM and DM - $s0 RF $s1 DM Flush this instruction RF $t1, $s4, $s0 ... slt $t3, $s2, $s3 IM slt $s2 RF $s3 slt 64 & RF DM $t3 RF 12 Handling Data and Control Hazards CLK Control Unit 31:26 5:0 CLK CLK RegWriteD RegWriteE RegWriteM RegWriteW MemtoRegD MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM ALUControlD2:0 ALUControlE2:0 Op ALUSrcD ALUSrcE Funct RegDstD RegDstE BranchD PCF EN A InstrD RD 25:21 A1 WE3 CLK = RD1 0 20:16 A2 A3 WD3 RD2 0 Register File 20:16 15:11 4 Sign Extend 0 SrcBE 1 RsD RsE RtD RtE RdE RdE ALUOutM WriteDataM WriteDataE 25:21 15:0 00 01 10 1 WE SrcAE 00 01 10 1 Instruction Memory + A RD Data Memory WD ReadDataW ALUOutW 0 WriteRegE4:0 WriteRegM4:0 1 0 WriteRegW 4:0 1 SignImmD SignImmE + <<2 PCPlus4D CLR CLR EN PCPlus4F PCBranchD RegWriteW RegWriteM MemtoRegE RegWriteE ForwardBE ForwardAE FlushE ForwardBD ForwardAD BranchD ResultW StallD 1 PC' StallF 0 PCSrcD EqualD CLK ALU CLK CLK Hazard Unit 13 Next Time • Memory-mapped I/O 14