Transcript Document

Preliminary LumiCAL
FEE Specification
Presented by Alexander Solin
NC PHEP
[email protected]
FCAL collaboration meeting, February 12-13, 2006,
Krakow (INP PAS), Poland
Contents


Preliminary LumiCAL FEE Specification
ASICs for FCAL detectors prototypes (main parameters
measurement setup, bench and beam tests)
February 12-13, 2006, Krakow
A.Solin
2
Preliminary LumiCAL FEE Specification
February 12-13, 2006, Krakow
A.Solin
3
Estimation of the pad Si-sensor
capacitancies
295pF/1413 sq. mm
15 deg
Rough segmentation parts
98pF/471 sq. mm
10 pads
B
80 mm
280 mm
15 deg
137pF/655 sq. mm
Fine segmentation part
42pF/201 sq. mm
22 pads
B
80 mm
280 mm
Cmax/Cmin=295pF/42pF=7
February 12-13, 2006, Krakow
A.Solin
4
Estimation of the strip Si-sensor
capacitancies
30 deg
For the bonded concentric strips:
Cmin=168 pF, Cmax=571 pF
28pF/133 sq.mm
95pF/455 sq.mm
64
concentric
strips
B
80 mm
280 mm
120 radial strips
3 deg
B
80 mm
395pF/1885 sq. mm
280 mm
Cmax/Cmin=395pF/28pF=14
The large difference of capacitance is problem for a
preamplifier noise optimization.
February 12-13, 2006, Krakow
A.Solin
5
Estimation of the maximum Si-sensor
charge collection
(1-1000)MIP channel signal range
from B.Pawlik’s talk
Cfb=3.2pF
2V
1000MIP
CSP
February 12-13, 2006, Krakow
A.Solin
6
LumiCal Si-sensor parameters
Material
Si
Think, 
500
si
11.8
Depletion voltage, V
155
Collection charge time, ns
28
MIP,e
40000
Capacitance range calculation
(look previous pictures )
Minimum value
Maximum value
Pad option
42pF
295pF
Strip option isolated concentric sectors
28pF
395pF
168pF
571pF
bonded concentric strips
February 12-13, 2006, Krakow
A.Solin
7
LumiCAL ASIC requirements
Signal to Noise Ratio (SNR)
5
Maximum ENC, e
8000
Maximum signal, MIP
1000
Dynamic range, bit
12-13
Shaping time, ns
70
Amplitude output, V
2
Gain, mV/fC
0.31
Channel structure of the first prototype
Preamplifier - Shaper
Number of channels per chip (rough estimation)
Detector mounting surface area, cm2
3956 (for 22.5 cm detector length)
Chip mounting surface area, cm2
4
Total number of chips
989
Number of channels per chip
Pad option
12
Strip option
14 (4 in case of bonded concentric strips)
Number of channels per chip fixed by tile size
22 (cheap package), 44
February 12-13, 2006, Krakow
A.Solin
8
ASIC technologies
Minsk
1.5µ design rules Bi-JFET
0.8µ design rules CMOS
0.6µ design rules Bi-CMOS
Leading European and Asiatic FABs
up to deep submicron design rules (if it
is reasonable)
Next four pictures can help to estimate noises of frond end electronics. Calculations are
done for Bi-JFET technology (see picture).
Same calculations can be done for other technologies. Preamplifier noises will be similar to
the presented calculations.
February 12-13, 2006, Krakow
A.Solin
9
Capacitance of Si-sensor vs its area
572pF
28pF
February 12-13, 2006, Krakow
A.Solin
10
ENC vs preamplifier power consumption
8000e
February 12-13, 2006, Krakow
A.Solin
11
ENC vs shaping time
8000e
February 12-13, 2006, Krakow
A.Solin
12
ENC vs Si-sensor Capacitance
572pF
February 12-13, 2006, Krakow
A.Solin
13
ASICs for FCAL detectors prototypes
(main parameters measurement setup, bench and
beam tests)
February 12-13, 2006, Krakow
A.Solin
14
Tetrode-BT, Tetrode-JFET ASICs
1996 year, CMS ECAL
Two designs CSP were made in Minsk NC PHEP with slightly
different circuits for amplifying of signals from Hamamtsu R2149
vacuum phototetrode:
“TETRODE-BT” with bipolar input transistor;
“TETRODE-JFET” with p-JFET input transistor.
February 12-13, 2006, Krakow
A.Solin
15
Design requirements to Tetrode CSPs
Hamamtsu R2149 parameters:
Ca
15pF
Anode dark current
Typical gain (HV= -900V, B= 0 T)
Quantum eff. at 500 nm
0.1 nA
30
10%
CSP requirements:
ENC, e
<1000
Dynamic range, bit
Output signal width (base-to-base), ns
February 12-13, 2006, Krakow
A.Solin
13
100ns
16
CSP based on Tetrode JFET
ENC=320e+18e/pF, Tp=800ns
ENC vs Vsupplies at Cd=0
Tetrode JFET based CSP
600
500
ENC, e
400
300
200
100
0
5
6
7
8
9
10
Vsupply, V
ENC vs Cd at Vsupplies=+/-8V
Tetrode JFET based CSP
2000
1800
1600
ENC, e
1400
1200
1000
800
600
400
200
0
0
20
40
60
80
100
Cd, pF
February 12-13, 2006, Krakow
A.Solin
17
AS01PDA, AS01T ASICs
2002 year, TESLA THCAL
Next AS01PDA ASIC were designed and manufactured in Minsk
NC PHEP for amplifying of signals from photodetectors.
The AS01PDA ASIC is a development of the “Tetrode BT” design
line. It additionally contains a shaper and shaper gain control stage.
February 12-13, 2006, Krakow
A.Solin
18
AS01PDA main parameters
Number of channels
1
Circuit structure
Preamplifier + Shaper +
50 Ohm Driver
Additional property
Shaper Gain Control
Shaper peaking time
90ns
Max. Gain
9mV/fC
ENC, e
1000+14.1e/pF
Shaper output
+/-1.5V
Power consumption
18mW
Package
SOP16
February 12-13, 2006, Krakow
A.Solin
19
AS01PDA block diagram
Preamplifier-
Shaper-
50 Ohm Driver
Signal input
(In)
Positive
output
(Op)
Ct 0.2pF
Test input
(In_t)
Negative
output
(On)
Bias block
Reference level
(Vref)
Gain control
(Gain_ctrl)
February 12-13, 2006, Krakow
A.Solin
20
AS01PDA tests


October, 2002
Output signals were digitalized with theTDS3032 scope.
Vout, V
AS01PDA ASIC response at Vcc=+6V
Ctest=1.2pF, Vin=45mV, Gain=3.5mV/fC
-1,00E-06
0,05
0
-0,05
-0,1
-0,15
-0,2
-0,25
-5,00E-07 0,00E+00
5,00E-07
1,00E-06
1,50E-06
Cd=0
Cd=68pF
Time, s
February 12-13, 2006, Krakow
A.Solin
21
AS01PDA noise curves

February, 2006
Noise is measured with the Infiniium 54830B scope.
ENC vs Cd and Vcc
ENC = 14,123e/pF + 1000e
5000
4500
4000
5V
3500
ENC, e

6V
3000
7V
2500
8V
2000
9V
1500
Trend line
1000
500
0
0
50
100
150
200
250
300
Cd, pF
February 12-13, 2006, Krakow
A.Solin
22
ASIC for large capacitance detectors
AS01T is optimazed for using with large capacitance detectors.
 It has the same structure as AS01PDA.
 The package is the same too.
 Both chips (AS01T and AS01PDA) are placed on the same wafer
and are manufactured in one process.
ENC vc Cd
AS01T
ENC of AS01PDA, AS01T ASICs
ENC = 6,6343e/pF + 2159,1e
10000
9000
8000
12000
ENC, e
8000
6V
6000
9V
Trend line
4000
ENC, e
10000
7000
6000
5000
4000
3000
6V_AS01PDA
6V_AS01T
2000
1000
0
2000
0
0
200
400
600
800
1000
1200
0
Cd, pF
February 12-13, 2006, Krakow
A.Solin
200
400
600
800
1000
1200
Cd, pF
23
Conclusion
The next steps of development of FEE for FCAL



Making of readout electronics for immediate beam tests (Tetrode,
AS01 ASICs)
Qualification of LumiCAL ASIC specification and design of new
prototype of 22 channel preamplifier-shaper ASIC for amplifying of
Si-detector signals.
Creation of multichannel readout electronics for larger FCAL
prototypes.
February 12-13, 2006, Krakow
A.Solin
24