Transcript Business Trends and Design Methodologies for IP Reuse

CAD Techniques for IP-Based
and System-On-Chip Designs
Allen C.-H. Wu
Department of Computer Science
Tsing Hua University
Hsinchu, Taiwan, R.O.C
{Email: [email protected]}
Outline
 Introduction
 Basic synthesis tasks
 Codesign of embedded systems
 FPGA synthesis and rapid prototyping
 IP-reuse design methodologies
 System-on-chip design methodologies
 HDL-based layout synthesis methodologies
Computer-Aided Design (CAD)
 Why?
 What?
 How?
Human-Centric Design Methodologies
 Designers are the creator of designs.
 Designers are artists.
 Designers pursuit the state of arts.
 Free styles with less discipline.
 May not be efficient on handling complex
designs.
 May not be effective on shortening the
design cycle.
Human Vs. Computer (Automation)
 Human is good at innovating creation.
 Human is not good at handling tedious and
repetitive tasks.
 Computer is good at handling tedious and
repetitive tasks, at least it will never complain
about it.
Why needs CAD?
 Design is getting more and more complex.
 Try to develop an error-prone design?
 Time-to-market pressure.
What is CAD?
 CAD = Computer-Aided Design.
 CAD will never be in the leading role of a
design process!!! Just a supporting role.
 Any techniques, methods, solutions which
are used solve a problem in a design
process.
How to apply CAD?
 Understand the design process.
 Identify the problems which need CAD
supports.
 Correctly define the problem and then solve
it.
A Typical System Design Process
Idea
System
Hardware
Software
Chips
OS
Application SW
System board
A Typical Chip Design Process
Chip spec.
RTL design
Logic design
Gate-level design
Layout
Silicon Compilation
 Compiler: converting a high-level source
code to a object code.
 Silicon compiler: converting a high-level
source code (system/chip description) to a
piece of silicon.
Synthesis
 Synthesis is a process which converts a
design from one domain to another
 System-level synthesis
 High-level (Behavioral) synthesis
 RTL synthesis
 Logic synthesis
 Layout synthesis
 HDL-based synthesis
The Y Chart
Behavioral System level
Structure
CPU,Mem
System spec.
Ckt level
Transformation
(Synthesis)
Chip/Board
Physical
Design Level
Behavioral
Structure
Physical
System Spec.
CPU, Mem.
Chip/board
Algorithm
Processor
Block/chip
RTL spec.
ALU, Reg. Etc.,
Macro-cell
Boolean Eqn.
Gate, FFs
Std. Cell
Differential Eqn.
Transistor
Polygon
Transitions in the Y Chart
Behavioral
Synthesis
Structure
Analysis
Optimization
Generation
Extraction
Physical
System-Level Synthesis
 Inputs: Design functionality (e.g., instruction
of a computer) and a set of design
constraints or requirements.
 The transition from a system-level
specification to one or more subsystem
descriptions at the algorithmic level (a set of
communicating concurrent processes,
together with a behavioral description at the
algorithmic level for each subsystem).
High-Level Synthesis
 Starting point: a behavioral description at the
algorithmic level, which defines a precise
procedure for the computational solution of a
problem. No notion of “CLOCK”.
 Outputs: controller and datapath.
 Time/area tradeoff.
RTL-Level Synthesis
 Inputs: an RTL netlist and a set of design
constraints.
 Each component in the netlist is described
either in behavioral, structural, or logic level.
 Controller synthesis: the transition from
controller behavior to structure.
 Module generation.
Logic-Level Synthesis
 Inputs: Boolean functions and FSMs.
 Outputs: the blocks of combinational logic
and storage elements.
 Logic minimization and optimization.
 Technology mapping.
Physical-Level Synthesis
 Inputs: a hierarchical gate-level netlist which
may contain hard macros and flexible soft
macros.
 Outputs: a layout.
 Floorplanning.
 Placement.
 Routing.
 Compaction.
HDL-Based Synthesis
 Why? What? How?
 VHDL and Verilog: originally a simulationbased language.
 Programming languages => hardware!
 Syntax and semantics gaps.
 Compilation is the key to the HDL-based
synthesis.
Other Design Issues
 Design entry.
 Design verification and validation:
- simulation
- formal method
- logic emulation
- rapid prototyping
- design rule checking
 Testing
Basic Synthesis Tasks
The Specification Language Problem
 Many Hardware Descriptive Languages
(HDLs): VHDL, Verilog, AHPL, ISP, PMS which
are derived from general programming
languages, e.g., ADA, ALGOL, C, and
PASCAL.
 All general programming languages can be
used for system-level simulation at
behavioral-level.
 No single language can cover the software
and hardware spectrum!!!!
 CASE problem!!!
Behavioral Transformations
 Optimizing transformations:
- Procedure in-line expansion
- Loop unrolling
- SELECT (IF & CASE) transformations
 Processes: concurrent execution.
 Interprocess communication:
synchronization issues
 Similar to OS problem!
Communications
 Mapping the logical communication structure
onto a physical communication structure.
 Synthesis of communication protocols.
System-Level Partitioning
 Hardware-software codesign.
 A lot of academia studies in this area!!!
 The key to the success is an accurate
estimation engine to support the partitioning
procedure!!!
Design Exploration
 Time/area tradeoff.
 Architectural-level exploration.
 Memory hierarchy and organization.
 System-level early design planning.
 Design estimation issues.
The Classical High-Level Synthesis
Tasks
 Design representation issues.
 Behavioral transformations.
 Allocations.
 Scheduling.
 Binding.
 Estimation and design exploration.
 Why after a decade of intensive research
effort high-level synthesis has not yet been
accepted by industry????