Transcript Slide 1
A SBST Approach
Topic:
Automatic generation of a „Software Based Self Test“ SBST
for simple processors, based on structural and functional
information
Tobias Koal
Institute of Computer Science
BTU Cottbus
Outline
1. Motivation
2. Basics
3. Conception
4. Implementation
5. Results
6. Summary + Outlook
7. Questions?
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Motivation
The test of IC‘s is an essential element during production
Sometimes cyclic field tests are as crucial as production
tests
Offline test => unfavourable, because device isn‘t able to fulfil its
function
Online test => more suitable, because device can do a cyclic
selftest and is still able to switch to its normal mode, in case of
an interrupt
Idea: self test with help of software
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Motivation
advantages:
Test of the IC during its normal operation speed => „at-speed“
No extra testequipment
No additional testhardware
Avoidance of the „Overtesting Problem“
Use both as production and as field test
disadvantages:
More effort during test development
Probably poorer in fault coverage than other structural test methodologies
like BIST
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Basics of SBST
Execution of a „normal“
instruction sequence
Adjust and observe faults
with this sequence of
instructions
Analysis of results can be realized by the routine or with
extern approaches
Difficulty: The generation of a „normal“ instruction
sequence, which is able to specifically test a circuit for
structural faults.
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Conception
input:
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Processor model (VHDL
netlist)
Description of the
instruction set
Partition of the design in
combinational blocks
Acquisition of functional
control limitations of each
combinational block
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Conception
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Construction of adequate
software templates
Creation of functional test
pattern
Mapping of test patterns
to software templates
Faultsimulation of
complete selftest software
output: valid test software
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Implementation
Find limitations of the input
controls
Not all input combination are
implemented
Some input values of a register may
have dependences to other registers
Implement the software template
Example template for the shown
ALU:
Set [OP-A] {data};
Set [OP-B] {data};
{ALU-OP} [OP-A] [OP-B];
Save [RESULT] MEM;
Save [FLAG] MEM;
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Implementation
Automatic Test Pattern Generation ATPG
Without limitations on the ATPG process, test patterns can be
generated which are functional invalid
For that reason some additional constraints are required
These constraints represent the functional limitations of the
circuit
ATPG functions & constraints
add atpg functions u1 AND I0 I1 I2 I3 I4
add atpg functions u2 AND ~I0 ~I1 ~I2 ~I3 ~I4
add atpg functions u3 AND I0 I1 I2 I3 ~I4
add atpg functions unused OR u1 u2 u3
add atpg constraint 0 unused
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Implementation
Mapping of the
generated test
pattern to the
created software
templates
This process was
automatied
completely by a
new tool called
ASM-builder
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Implementation
String together all filled SW- Templates to recieve a
coherent software
It might be, that additional instruction are required, to
guarantee that the software is executable
Simulation of the sw routine with injection of all possible
faults to get the actual faultcoverage
Important, because of the possibility of fault masking
Software is also able to detect more faults than expected
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Architecture of the test vehicle T5016tp
16Bit RISC architecture
Hardwired controllogic,
arithmetical and logical
base operations
Special testextensions
(LFSR/MISR structures,
parallel/serial I/O
interface for scan test
solutions)
64kb memory size
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Memory
clk
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Control
path
I/O
control word
Data path
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Results
(single stuck-at of all datapath modules)
ALU
Shifter
Multiplexer
LFSR/MISR
657 / 656
362 / 306
3450 / 3194
1298 / 1296
FC / TC scantest (%)
99,85 / 100
84,53 / 100
92,58 / 100
95,59 / 95,72
FC / TC manual SBST
(%)
95,74 / 95,88
82,32 / 97,39
86,14 / 93,16
94,34 / 94,98
FC / TC automatic
SBST (%)
99,54 / 99,70
84,53 / 100
92,23 /99,63
94,22 / 94,37
Memory requirements
auto. SBST (16Bit
words)
191
136
1106
511
Elapse time (clock
Cycles)
433
293
2509
1221
Number of faults /
structural testable
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Results
(transition faults of all datapath modules)
ALU
Shifter
Multiplexer
LFSR/MISR
986 / 985
630 / 492
6776 / 6264
1940 / 1938
FC / TC scantest (%)
89,96 / 90,05
60,95 / 78,05
91,99 / 99,51
89,90 / 89,99
FC / TC manual SBST
(%)
66,23 / 66,29
50,16 / 64,22
42,15 / 45,59
65,57 / 65,63
FC / TC automatic
SBST (%)
73,02 / 73,10
51,75 / 66,26
75,59 / 81,77
66,39 / 66,46
Memory requirements
auto. SBST (16Bit
words)
245
133
1443
283
Elapse time (clock
Cycles)
583
317
3375
702
Number of faults /
structural testable
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Results
(single stuck-at faults for the T5016tp)
Control path
Data path
Fault count / structural testable
3297 / 3182
9197 / 8880
FC / TC Scantest (%)
92,87 / 96,23
93,37 / 97,07
FC / TC manual SBST (%)
83,01 / 86,02
92,12 / 95,41
Memory requirements man. SBST (16Bit
words)
1474
Elapse time (Clock cycles)
3163
FC / TC automatic SBST (%)
84,50 / 87,55
93,20 / 96,53
Memory requirements auto. SBST (16Bit
words)
4775
Elapse time (Clock cycles)
13795
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Summary
SBST for single stuck-at faults are in the range of scan
test approaches
SBST for transition faults don‘t reach the qualities of
scan test approaches
SBST is an attractive test approach, because no
addtional test equipment or test hardware are required
SBST is realizeable for simple processor structures
This approach could be used as alternative test
methodology for simple IC structures
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Outlook
At the moment no more research on this project is
planed, but different extenstion are possible:
More automation of the presented concept
Many extension are thinkable
Optimization of the presented approach
Adaption of this approach to other architectures
Adaption to other fault models
Low power test software generation
Short elapse times
Less memory requirements
Adaption of the SBST approach for diagnose
Software test friendly design of processors
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Finish
Thank You for your attention!
questions?
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