Transcript MonolithIC 3D ICs
MonolithIC 3D ICs
November 2012 MonolithIC 3D Inc. , Patents Pending MonolithIC 3D Inc. , Patents Pending 1
Monolithic 3D RC-JLT (Recessed-Channel Junction-Less Transistor )
MonolithIC 3D Inc. Patents Pending 2
Technology
Monolithic 3D IC technology is applied to producing monolithically stacked low leakage Recessed Channel Junction-Less Transistors (RC-JLTs).
Junction-less (gated resistor) transistors are very simple to manufacture, and they scale easily to devices below 20nm: • Bulk Device, not surface • Fully Depleted channel • Simple alternative to FinFET Superior contact resistance is achieved with the heavier doped top layer. The RCAT style transistor structure provides ultra-low leakage.
Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down.
MonolithIC 3D Inc. Patents Pending 3
RCJLT – a monolithic process flow
Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC
Oxide ~100nm N+ N++ Wafer, ~700µm P MonolithIC 3D Inc. , Patents Pending 4
Implant Hydrogen for Ion-Cut
H+ Oxide ~100nm N+ N++ Wafer, ~700µm P MonolithIC 3D Inc. Patents Pending 5
Hydrogen cleave plane for Ion-Cut formed in donor wafer
Oxide ~100nm N+ N++ Wafer, ~700µm P MonolithIC 3D Inc. Patents Pending H+ ~10nm 6
Flip over and bond the donor wafer to the base (acceptor) wafer
Donor Wafer, ~700µm P ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer H+ Base Wafer, ~700µm MonolithIC 3D Inc. Patents Pending 7
Perform Ion-Cut Cleave
~100nm N++ N+ 1µ Top Portion of Base Wafer Base Wafer ~700µm MonolithIC 3D Inc. Patents Pending Oxide 8
Complete Ion-Cut
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 9
Etch Isolation regions as the first step to define RCAT transistors
~100nm N++ N+ 1µ Top Portion of Base Wafer Oxide MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 10
Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP
~100nm N++ N+ 1µ Top Portion of Base Wafer Oxide MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 11
Etch RCAT Gate Regions
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Gate region Oxide 12
Form Gate Oxide
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 13
Form Gate Electrode
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 14
Add Dielectric and CMP
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 15
Etch Thru-Layer-Via and RCJLT Transistor Contacts
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 16
Fill in Copper
~100nm N++ N+ 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm Oxide 17
Add more layers monolithically
~100nm N++ N+ ~100nm N++ N+ 1µ Top Portion of Base (acceptor) Wafer Base Wafer ~700µm MonolithIC 3D Inc. Patents Pending Oxide Oxide 18
Benefits for RCJLT
• • • • 2x lower power 2x smaller silicon area 4x smaller footprint Layer to layer interconnect density at close to full lithographic resolution and alignment • • • • Performance of single crystal silicon transistors on all layers in the 3D IC Scalable: scales naturally with equipment capability Forestalls next gen litho-tool risk Also useful as Anti-Fuse FPGA programming transistors: programmable interconnect is 10x-50x smaller & lower power than SRAM FPGA • Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices MonolithIC 3D Inc. Patents Pending 19
RC-JLT flow: Summary
Create a layer of Recessed Channel Junction-Less Transistors (RC-JLTs), a junction-less version of the RCAT used in DRAMs, by activating dopants at ~1000 ° C before wafer bonding to the CMOS substrate and cleaving, thereby leaving a very thin doped stack layer from which transistors are completed, utilizing less than 400 ° C etch and deposition processes.
MonolithIC 3D Inc. Patents Pending 20