Transcript ECE-200, Spring 2000 Fundamentals of Intelligent Systems

Combinational Logic Design
digital systems are complex and sophisticated
Millions of gates
It is impossible to design each and every
implementation of functions from scratch.
Even seemingly simple expressions may turns
out to have not so simple implementations.
Fortunately, many expressions are
compositions of expressions we know and
whose implementations we can re-use and
combine.
Digital design Ed F. Deprettere Leiden University
Example: 9 input Odd Parity
Generator
Design a circuit with nine inputs and one output:
if number of 1’s in input is odd (even) then output is 1 (0)
F(0, 0, 0, 0, 0, 0, 0, 1, 1) = 0
F(1, 0, 1, 0,1,0,0,0,0)= 1
What about the truth table? It has 29 = 512 rows (!)
50% of these will have an odd number of 1’s :
256 minterms(!)
It turns out that all minterms are prime!
Conclusion:
9x256 = 2304 literals!
Digital design Ed F. Deprettere Leiden University
Parity generator and parity checker
Recall XOR function:
X  Y  Z = m(1, 2, 4, 7)
Such functions are special. They are called Odd Functions. Why?
n
Half the number of minterms (2 /2) have an odd number of 1’s
and they all appear in the SOP form of the many-variable XOR
Y
No symplification is possible!
XYZ+XYZ+XYZ+XYZ
An odd number of variables must be 1
X
1
1
1
1
Parity Generator P = X  Y  Z
Z
Parity Checker C = X  Y  Z  P MESSAGE = (X,Y,Z,P)
Total number of 1’s even
Digital design Ed F. Deprettere Leiden University
Example: 9 input Odd Parity
Generator (cont’d)
XOR(X,Y)
computes odd parity of two inputs (X, Y)
XOR(XOR(X, Y), Z) computes odd parity of three inputs (X,Y,Z)
Thus, odd parity of 9 inputs is generated by:
X0
X1
X2
X3
X4
X5
X6
X7
X8
Digital design Ed F. Deprettere Leiden University
Combinational Logic Design
How to design combinational circuits?
Use fundamental circuits called basic blocks
Re-use basic blocks to design new circuits
Use hierarchy
Use tools for Computer Aided Design
Digital design Ed F. Deprettere Leiden University
Example: The 9-variable PG
9-odd
X
Z
9
X0
X1
X2
X3
X4
X5
X6
X7
X8
9-input odd
function
System Diagram
X0
X1
X2
A0
A1 B
A2
X3
X4
X5
A0
A1 B
A2
X6
X7
X8
A0
A1 B
A2
A0
A1 B
A2
Z0
Circuit Design for Unit
A0
Z0
A1
B
A2
Circuit Symbol for Unit
Logic Diagram for Module
Digital design Ed F. Deprettere Leiden University
Computer-Aided Design
Schematic capture tools
Graphical editors to support drawing and interconnecting
of blocks at all levels of the hierarchy.
Libraries
Provide lots of graphics symbols from gates to basic
blocks and more.
Logic Simulators
To evaluate and validate the functional behavior and
timing behavior of your design.
Logic Synthesizers
To optimize the design for minimum area, delay, and
power in the realization.
Digital design Ed F. Deprettere Leiden University
Hardware Description
Languages
HDL is a programming language used to describe hardware
behavior and structure (structural description).
It can deal with parallelism. It is a powerful alternative to
schematics.
Two standards: VHDL and Verilog
Unfortunately, I can not teach you this language(s) because
of lack of time.
Digital design Ed F. Deprettere Leiden University
Analysis: is circuit
behaving well?
A circuit is designed to inplement a function.
Question: is the design correct?
Answer: find the circuit’s actual input-ouput relation and see
whether it is the desired function.
How?
1. Label gate outputs that depend on input variables directly
2. Write Boolean functions for these gate outputs
3. Repeat process until final output is obtained
Alternatively: build up Truth Table instead of function.
Digital design Ed F. Deprettere Leiden University
Finding the circuit’s function
T1=B'C
T2=A'B
B'D
F1  T3  T4  A  B' C  A'BD' AD  B'D
T3=T1+A=A+B'C
T4  T2  D  (AD)D  ABD AD  B'D
T5  T2 D  A'B  D
F2 = T5 = A'B + D
Digital design Ed F. Deprettere Leiden University
Truth Table from Circuit
1. Write input rows (2n, where n is the number of inputs)
2. Break circuit up into blocks, label each block with symbol
3. Obtain truth table for blocks with functions that depend on
input variables only
4. Go on to obtain truth table for blocks with functions that
depend on previously defined inputs and block outputs,
until columns for all circuit outputs are found.
Digital design Ed F. Deprettere Leiden University
Example: Circuit to Truth Table
C  XY  XZ  YZ
T1  XYZ
T2  X  Y  Z
T3  CT2
Digital design Ed F. Deprettere Leiden University
S  T1  T3
Circuit to Truth Table (cont’d)
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
T1 T2 T3
0 0 0
0 1 1
0 1 1
0 1 0
0 1 1
0 1 0
0 1 0
1 1 0
S
0
1
1
0
1
0
0
1
C  XY  XZ  YZ
T1  XYZ
T2  X  Y  Z
T3  CT2
Digital design Ed F. Deprettere Leiden University
S  T1  T3
Let’s Design Circuits
We know by now how to do, don’t we?
1. Define inputs and outputs to circuit, specify names
2. Derive truth table that defines the required relationship
between inputs and outputs
3. Obtain simplified Boolean expressions for output functions
4. Draw logic diagrams.
5. Check correctness of the design.
Example 3-1 on page 106 is a simple illustration
( read it!)
Digital design Ed F. Deprettere Leiden University
Code Convertors
Code converters translate a particular binary code to another.
Frequently used converters are:
Decoders convert n-bit words to m 2n unique outputs
? Encoders perform inverse operation of decoder.
Multiplexers select one of many inputs to a single output
Demultiplexers performs inverse operation of multiplexer.
min or max terms
structurally
Identical to
decoder
Digital design Ed F. Deprettere Leiden University
Decoders
Recall, A decoder is a circuit that has n inputs and m  2n outputs
Terminology:
2-to-4 line decoder, 3-to-8 line decoder, …
Outputs are minterms (or maxterms) of the inputs
Example: 2-input decoder. Inputs: A1, A0. Outputs: D3, D2, D1, D0
A1
0
0
1
1
A0
0
1
0
1
D3
0
0
0
1
D2
0
0
1
0
D1
0
1
0
0
Digital design Ed F. Deprettere Leiden University
D0
m0
1
0
0
0
Decoder is basic block
Again, decoders are basic blocks. We use them over and over
again – as we shall see.
You’ll find this symbol in library
A0
A1
E
20
21
E
0
1
2
3
D0
D1
D2
D3
2-to-4
Decoder E is zero
enable bit: all D zero whenever
Digital design Ed F. Deprettere Leiden University
Design
enable bit instructs decoder when it is to be active
all outputs are zero if enable bit is zero
Truth Table
E
0
0
0
0
1
1
1
1
A1 A0 D3D2D1D0
0 0 0 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 1 0 0 0 0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
2-to-4
0
01
0
0
0
0
01
Enable bit
Example:
10
D0 = (A0 + A1 + E')' = A0 ' A1 ' E = m0•E
Digital design Ed F. Deprettere Leiden University
Full adder with decoder
As we know, the full adder has
Three inputs: two bits to be added and a carry-in
Two outputs: sum and carry out
Logic Functions
S(X, Y, Z) = ∑m(1,2,4,7)
C(X, Y, Z) = ∑m(3,5,6,7)
Idea: Decoder offers all
minterms. So:
OR minterms in S
and C from decoder.
20
21
22
0
1
2
3
4
E
5
6
3-to-8 7
Decoder
Digital design Ed F. Deprettere Leiden University
Bigger decoders from small once
Given:
2-to-4 decoders
Required: 3-to-8 decoder
Solution: each decoder
realizes half the
minterms. Enable
selects which decoder is
active:
A2 = 0: enable top decoder
A2= 1: enable bottom
decoder
Digital design Ed F. Deprettere Leiden University
Encoders
Recall: encoder is inverse operation of decoder. From minterms to binary
It has 2n inputs Dk, and n outputs Al.
the n outputs form together the binary code of the one input that is 1
Consider a base-4 number (B3B2B1B0)4. To convert to binary, start with B0.
If B0 = N (0, 1, 2 or 3), set DN to 1 and all other Dk to zero. Output is binary
N.
Truth Table of 4-to-2 Encoder
is a minterm
table!
(D3 m3)
D3
0
0
0
1
Inputs
D2
D1
0
0
0
1
1
0
0
0
D0
1
0
0
0
Outputs
A1
A0
0
0
0
1
1
0
1
1
D2 = 1
What should happen when two inputs are 1?
Not very useful
Digital design Ed F. Deprettere Leiden University
Undefined!
Priority Encoder
If there are k inputs, then the code has ( log2k ) outputs plus
a validity bit V.V = 1 only if one or more inputs are1.
If V=0, then result is invalid
This
a condensed
truth
table
Else, only
theisleft-most
1 in the
input
row will be “seen” by
corresponding to 16-row
the encoder.
table. If you understand it, then
Truthunderstand
Table: 4-to-2don’t
Priority
Encoder
you really
cares
D3
0
0
0
0
1
Inputs
D2
D1
0
0
0
0
0
1
1
X
X
X
D0
0
1
X
X
X
Outputs
A1
A0
X
X
0
0
0
1
1
0
1
1
Digital design Ed F. Deprettere Leiden University
V
0
1
1
1
1
Multiplexer
Recall: a multiplexer selects one from many inputs. It is a
very usefull circuit.
It has
n select inputs: S0 ... Sn-1
2n data inputs: D0 ... D
(2 1)
n
1 enable input E
One output Y
If E = 0, Y= 0
Else, Y = Dk, where k =(Sn-1Sn-2 …S0)
Digital design Ed F. Deprettere Leiden University
4-to-1 Multiplexer
"Truth Table"
S1
X
0
0
1
1
select
S0
X
0
1
0
1
E
0
1
1
1
1
Y
0
D0
D1
D2
D3
enable output
Actual truth table has 27 = 128 rows
D0, …,D3 ; S0, S1; and E
Digital design Ed F. Deprettere Leiden University
4x1 MUX
S0
S1
0
1
2
3
4 X 1 MUX
X0
X1
Y
X2
.
X3 = E D3S1S2
X0 = E AND D0S1S0
X1 = E AND D1S1S0
X2 = E AND D2S1S0
The four underlined terms remind me of a decoder!
Digital design Ed F. Deprettere Leiden University
2-input –bit bus
A bus is a communication path to which several units have access, not at the
same time. An arbiter is regulating the traffic. If two data words ASK for the bus,
only one get it.
S
4
A
Circuit
Diagram
4
B
2x4
MUX
4
Y
E
System Diagram
All A (S=0) or all B (S=1)
Digital design Ed F. Deprettere Leiden University
4x1 MUX from 2x1 MUX'es
S1 S0 Y
0
0
1
1
Digital design Ed F. Deprettere Leiden University
0
1
0
1
D0
D1
D2
D3
Implementing functions with MUX
We already used decoders to implement functions. A MUX is
essentially a decoder (with the mux’s external OR gate absorbed).
n
n selection inputs, and 2 data inputs – one for each minterm
related to the selection inputs. Fine, but we can do with n-1 s-inputs!
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
F
0
1
1
0
0
0
1
1
Let’s implement F(X,Y,Z) = m(1,2,6,7)
F is either Z, or Z, or 0, or 1 and (X,Y) is
uniquely determining which one of these.
So, take X and Y as the 2(!) selection bits,
and Z, Z,0 and 1 as the 4 corresponding
data bits.
X = S1, Y = S0, Z = D0, Z = D1, 0 = D2, 1 = D3, F = Out
Digital design Ed F. Deprettere Leiden University
The Demultiplexer
Recall: a demultiplexer performs the inverse function of the MUX.
Input: a single data line D
Output: 2 data lines D0, …, D(2n -1)
Operation: bring input to one of the outputs. Use n selection bits
S0, …S(n-1) to determine which output line.
S0
S1
D0
D1
D2
D0 = (S0 + S1 + D')' = S0 ' S1 ' D = m0•D
D3
D
Digital design Ed F. Deprettere Leiden University
Programmable Logic
In general, Programmable Logic Array (PLA)
consist of two arrays:
An AND array, and
An OR array.
Array logic
“Programmable”
Two-input AND
AND array
Digital design
Three-input
OR
Ed F. Deprettere
Leiden University
OR array
Types
1. AND array is fixed (decoder), OR array is
programmable
2. AND array is programmable, OR array is fixed
3. AND array and OR array are programmable
The names: programmable logic devices:
1. Programmable Read-only memory
(PROM, EPROM, E PROM)
2
2. Programmable array logic (PAL) devices
3. Programmable logic array (PLA) devices
Digital design Ed F. Deprettere Leiden University
Read-only Memory (ROM)
k
A 2  n ROM stores 2
nonvolatile way.
k
words of n bits each in a
k
It consists of 1) a k-to-2 decoder and 2) a programmable OR array
0
0
1
1
2
5-to-32.
2
decoder
.
3
.
4
31
Address in
Data out
7
6
5
To be considered as having 32 inputs
32 lines = 32 inputs/OR, 8 ORs
4
3
2
1
0
Each decoder out connected to one
of the inputs of each OR gate
32  8=256 programmable connections.
Digital design Ed F. Deprettere Leiden University
ROM design
XYZ
F1
F2
F3
F4
000
001
010
011
100
001
000
011
000
010
000
010
100
100
000
01
00
10
00
11
0000
0101
0000
0010
1100
Three bits
0
1
2
3-to-8 3
decoder 4
x
x
three bits
three bits
(= Memory Word)
two bits four bits
Digital design Ed F. Deprettere Leiden University
Is a Truth table
12 bits
Prog’able Logic Array (PAL)
In a PLA, the decoder of the PROM is replaced
by an AND array.
P-term 1 connected
The AND array has the same function
P-term 2 connected
as the decoder: generating product terms.
k  m prog. connects
P-term 3 not connected
F1 = AB + AC + ABC
F2 = AC + BC
P-term 4 connected
2n  k progr. connects
Out is F1 (not F1)
k P-terms (four)
PLA Programming table.
1
AB
Inputs Outputs
(T) (C)
2
AC
Product terms A B C F1 F2
3
BC
1
1 0
1
4
ABC
0
2
1 1 1 1
1
3
1 1
1
F
C C B B A A
4
0 1 0 1
n inputs (three)
1
F2
A connected
When programmable by user, PLA is called field programmble.
m outputs (two)
B connected
Digital design Ed F. Deprettere Leiden University
C not connected
Prog’able Array Logic (PAL)
In these programmable devices, the OR array is fixed.
PALs are composed of a number of
PAL sections.
programmable
Each section consists of:
In
One buffer/inverter input

One buffer/inverter output feedback
One output
A k-wide AND-OR array (k programmable
AND gates and one fixed OR gate)
four programmable AND gate connections,
Out

Product terms cannot be shared among sections. Thus each output
(function) can be simplified by itself (unlike in PALs where you
want to share product terms).
The number of P-terms in a section is fixed. If you need more, use more sections
Digital design Ed F. Deprettere Leiden University
Address MUX2 MUX1
A2 A1 A0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
M2
M1
M0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
A2 A2 A1 A1A0A0M2M2
A2

MUX0
Example.
MUX2 = m(0, 1, 2, 4) = A 2 A0 + A 1A0
MUX1 = m(1, 3, 4) = A 2A0 + A 1A0
MUX0 = m(0, 1, 2, 4,5) = MUX2 + A 1A0
1
PAL Programming Table.
M0
2
3
A1

M1
4

A0
5

M2
6
Digital design
Ed F. Deprettere
P-term
1
2
3
4
5
6
A2 A1 A0 M2
1
1 0
0
1
0 0
0
0
0 1
A2 connected
A1 not connected
Leiden University
A0 connected
Output
M0
M1
M2
FPGAs
Most popular are Xilinx and Altera. See your
hands-on exercise implementations.
I’ll come back to them when we have seen
sequential circuits.
Programming FPGAs is all you have to master
to realize even very complicated digital systems
That’s exactly what you will master by the end
of the course.
Digital design Ed F. Deprettere Leiden University
Summary
Learned how to design combinational circuits
Learned how to analyse combinational circuits
Defined, designed and used important basic blocks called code
Converters:
n
Decoder : almost always with enable bit. Generates m  2
min (max) terms of the n variables input to it.
n-to-m line decoder
n
Multiplexer: takes data from one of 2 single-bit lines
selected through an n-bit input selection code.
n
2 -to-1 line multiplexer
essentially a decoder + an many-input OR gate
Demux: inverse MUX. Structurally identical to Decoder .
Digital design Ed F. Deprettere Leiden University
Recall: XOR is not a basic gate. We write F = X  Y and the
meaning is F is 1 if and only if X=1 or Y=1 but not both.
It is a shorthand for the following
Does it work?
F = [(X(XY))( Y(XY)) ] = [(X(X+ Y )) (Y(X + Y))]
= [(XY)(YX)] = XY+ XY
Digital design Ed F. Deprettere Leiden University
Managing Complexity
Hierarchical Design
A system consists of subsystems.
Subsystems consist of units or blocks, units consist of subunits, …
Top-down design
Partition a system into subsystems, subsystems into units, ….
When well done, the whole system is decomposed into basic blocks
that you have to design (or someone else has already done = library)
Composition
Interconnect basic blocks, subunits, units, subsystems correctly to
get the system design.
Use tools (computer) to assist you
Digital design Ed F. Deprettere Leiden University
Example: BCD to Seven Segment Code Converter
f
e
a
g
d
b
c
Activation patterns for digits 0 through 9
Input is BCD-code: Need four variables A, B, C, D
Outputs are seven functions to drive LED segments a-g
The seven
segments example
A=0, B=1, C=0, D=1 denotes "5“
convert (ABCD) =0101 to (abcdefg) = 1011011
Digital design Ed F. Deprettere Leiden University
Truth Tables
BCD Input
A
B
C
D
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
all other inputs
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)a
f b
g
e c
d
a
1
0
1
1
0
1
1
1
1
1
Seven-Segment Decoder
b
c
d
e
f
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
1
all zeros
Digital design Ed F. Deprettere Leiden University
g
0
0
0
1
1
1
1
0
1
1
Synthesize Function 'a'
EPI's: A'C, AAB'C'.
C
Other PI's: B'C'D', A'BD
B
A
D
Map for function 'a'
a = A'C+A'BD+AB'C'+B'C'D'
Digital design Ed F. Deprettere Leiden University
Verify Boolean Expression
for 'a'
a = A'C+A'BD+AB'C'+B'C'D'
A
B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A'C+A'BD+AB'C'+B'C'D'
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TRUE
FALSE
TRUE
TRUE
FALSE
TRUE
TRUE
TRUE
TRUE
TRUE
FALSE
FALSE
FALSE
FALSE
FALSE
FALSE
Digital design Ed F. Deprettere Leiden University