Transcript TELE9301 Switching Systems Design

UNSW
1
School of Electrical Engineering and Telecommunications
Implementing tries in RAM
Each node stored in one word, containing at most 3 ptrs:
• left: next rule if bit is 0
(rule=0=>no rule)
• centre: next rule if bit is 1
=0, =1, rule • right: rule if this is last matched bit
RAM
Addr. Content
1
2
3
4
5
6
7
8
9
10
2,3,0
0,4,a
5,6,d
7,c,0
e,0,0
8,9,0
10,0,0
f,g,0
h,i,0
b,0,0
a => to port X
b => to port Y
c => to port X
51C4*
...
(Only need right pointer if other 2 aren’t leaves. e.g. not
needed for nodes 8 and 9.)
Start search at node 1, continue until either:
• match leaf node, e.g. 011 matches c
• can’t progress past a node, then use previous best match, e.g.
0101 matches a en route to blockage at node 7.
1
0
1
2 a
3 d
4
7
10
b
Copyright
©
20/07/2015
Tim Moors
5
c
e
6
8
9
f g h
i
UNSW
2
School of Electrical Engineering and Telecommunications
e.g. Multi-bit variable-stride trie
Prefix
Next-hop
35
10*
7
01*
21
3
0000
0010
110*
9
1011*
1
0100
0001*
68
0110
01011*
51
00110*
3
1000
35
35
68
35
35
35
21
35
21
35
21
35
35
21
35
35
7
35
7
35
7
35
71
10001*
6
1010
100001*
33
1100
35
9
1110
9
35
35
35
10000000*
54
1000000000*
12
1000000011*
14
51DE*
128.252.153.160
1000 0000 1111 1100 1001 1001 1010 0000
step 4
step 3
step 2
step 1
*
3
21
21
51
51
7
7
33
6
54
7
12
54
7
54
6
7
14
Slide by V. Sivaraman based on example from D. Taylor et al: 'Scalable IP lookup
for programmable routers', Proc. Infocom, pp. 562-71, 2002
Copyright
©
20/07/2015
Tim Moors