Transcript Memory space of a typical system

Memory space of a typical system
Program code and initialization vectors
Stack and heap, variable storage
Hardware Computer Organization for the Software Professional
Arnold S. Berger
0xFFFFFE
IO Devices
RAM
512K x 16
Empty
Space
Empty
Space
0xF00000
Empty
Space
IO Devices
ROM
64K x 16
0x01FFFE
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Example: Assume a 24-bit addressing range, 16-bit wide data bus
- 24-bit addressing >> 16 Mbyte
Assume 1 Mbyte of RAM memory, 128KByte of ROM
0x000000
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1
Byte Packing
Word Address
000000
Byte 0 – Address 000000
Byte 1 – Address 000001
Byte 2 – Address 000002
Byte 3 – Address 000003
000004
Byte 0 – Address 000004
Byte 1 – Address 000005
Byte 2 – Address 000006
Byte 3 – Address 000007
000008
Byte 0 – Address 000008
Byte 1 – Address 000009
Byte 2 – Address 00000A
Byte 3 – Address 00000B
00000C
Byte 0 – Address 00000C
Byte 1 – Address 00000D
Byte 2 – Address 00000E
Byte 3 – Address 00000F
000010
Byte 0 – Address 000010
Byte 1 – Address 000011
Byte 2 – Address 000012
Byte 3 – Address 000013
FFFFF0
Byte 0 – Address FFFFF0
Byte 1 – Address FFFFF1
Byte 2 – Address FFFFF2
Byte 3 – Address FFFFF3
FFFFF4
Byte 0 – Address FFFFF4
Byte 1 – Address FFFFF5
Byte 2 – Address FFFFF6
Byte 3 – Address FFFFF7
FFFFF8
Byte 0 – Address FFFFF8
Byte 1 – Address FFFFF9
Byte 2 – Address FFFFFA
Byte 3 – Address FFFFFB
FFFFFC
Byte 0 – Address FFFFFC
Byte 1 – Address FFFFFD
Byte 2 – Address FFFFFE
Byte 3 – Address FFFFFF
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Memory organization (2)
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Memory organization usually depends upon the width of the processor data bus
- The 68000 is a 32-bit processor internally, but interfaces to a 16-bit data
bus
- All addresses are 32-bits internally, with 24-bits external (16M)
7
Bit
0
0x0000
S
T
R
I
N
G
15
87
0x00000
0x00001
Byte Addressable
memory for an
8-bit processor
with a 16-bit
addressing range
0xFFFE
0xFFFF
Bit
0
0xFFFFF
T
I
G
S
R
N
15
0x000000
Byte Addressable
memory for a
16-bit processor
with a 20-bit
addressing range
Intel 80186
Little Endian
0xFFFFE
Bit
0
87
0x000001
S
R
N
T
I
G
0xFFFFFE
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Byte Addressable
memory for a
16-bit processor
with a 24-bit
addressing range
MC68000
Big Endian
0xFFFFFF
3
Memory organization
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In byte-addressable systems, low-order address bits do the byte addressing
- Example: The 68000 has 23 external address lines and can address 224
bytes ( 0..16,777,215 ) or 223 words ( 0..8,388,607 )
- Address bit A0 is implied by two other signals, UDS and LDS
- Can be considered to be the byte selector bits for a word
addressing system, A1..A23
- For a 32-bit addressing system and a 32-bit data path ( long word )
address bits A2..A31 ( 0..1,073,741,823 ) address the word and address
bits A0,A1 address the byte of the word
31
A0
A1
24 23
1
1
16 15
87
0
1
1
0
Little Endian
0
0
0
31
A0
A1
24 23
0
0
87
16 15
1
0
0
1
0
1
1
Big Endian
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68000 Memory Access
D15
D8
D7
68000
Processor
D0
Byte Access
Note: A word access on a byte boundary would
require two memory operations to complete and
is not allowed in the 68000 processor.
A0=0: LDS=1, UDS=0
A0=1: UDS=1, LDS=0
Word Access
A0=0: LDS=0, UDS=0
A0=1: LDS=1, UDS=1
A1..A23
Lower Data Strobe (LDS)
Upper Data Strobe (UDS)
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Memory organization (4)
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Storing 32-bit values in a 16-bit external memory
EVEN BYTE
7
6
5
ODD BYTE
4
2
1
0
7
6
5
4
3
2
1
0
4
3
2
1
0
1 LONG WORD = 32 BITS
15
14
13
12
11
MSB
10
9
8
7
6
5
HIGH ORDER WORD
LONG WORD 0
LOW ORDER WORD
LSB
MSB
LONG WORD 1
LSB
MSB
LONG WORD 2
LSB
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Introduction to Assembly Language
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•
•
Every computer system has a fundamental set of operations that it can
perform
These operations are defined by the instruction set of the processor
- The instruction set is the atomic element of the processor
- All the complex operations are achieved by building sequences of these
fundamental operations
Assembly language is the human readable form of these instructions,
called machine language
Instead of writing a program in
machine language as:
We write the program in
assembly language as:
00000412 307B7048
00000416 327B704A
0000041A 1080
0000041C B010
000041E 67000008
00000422 1600
00000424 61000066
00000428 5248
0000042A B0C9
MOVEA.W
MOVEA.W
MOVE.B
CMP.B
BEQ
MOVE.B
BSR
ADDQ.W
CMPA.W
(TEST_S,PC,D7),A0
(TEST_E,PC,D7),A1
D0,(A0)
(A0),D0
NEXT_LOCATION
D0,D3
ERROR
#01,A0
A1,A0
*We'll use address indirect
*Get the end address
*Write the byte
*Test it
*OK, keep going
*copy bad data
*Bad byte
*increment the address
*are we done?
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Using labels
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•
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Label, a symbolic name given to a variable or a constant
- Usually refers to a memory address
- Must be defined in column 1
Labels make the program readable
- A program may be written without labels, but almost no one ever does it
- Labels allow the assembler program to automatically calculate addresses
- Avoids errors in addressing
Example, consider the following snippet of code:
TEST_LOOP
DONE
•
MOVE.B (A2),D6
CMPI.B #END_TEST,D6
BEQ
DONE
LEA
ST_ADDR,A0
LEA
END_ADDR,A1
JSR
DO_TEST
ADDA.W #01,A2
BRA
TEST_LOOP
STOP
#EXIT
Question: What does this instruction do?
*Let D6 test the patterns for done
*Are we done?
*We've done the 4 patterns
*Set up the starting address in A0
*Set up the ending address in A1
*Go to the test
*Point to the next test pattern
*Go back to the next location
*Test is over, stop
foo
BRA
foo
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*Huh?
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Hardware Organization of the MC68000
Holds address
of the next instruction
to be executed
Program Counter (PC)
32
Effective Address Register (EAR) 32
If necessary
Holds the address
of memory reads/writes
Memory
and I/O
Interface
Control
Pipeline
Internal Bus
External
Bus
Instruction
Register(IR)
16
Instruction
Decode
and Control
General Registers
D0..D7
A0..A6
A7= User Stack pointer (USP)
A7’=Supervisor Stack Pointer(SSP)
32
Temporary Register
Holds first word
of currently
executing instruction
32
Holds operands or
intermediate results
Performs all logical
or arithmetic
operations
( ADD, SHIFT, etc. )
Arithmetic and Logic Unit
(ALU)
8
CCR
SR
32
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Holds result of ALU
Operations
9
Programmer’s model of an MC68000
MSB
31
16,15
8,7
MSB
31
LSB
0
D0
D1
D2
D3
DATA
REGISTERS
LSB
0
16,15
A7 (USP)
USER STACK POINTER
31
0
PC
D4
D5
D6
D7
PROGRAM COUNTER
0
7
CCR
MSB
ADDRESS
REGISTERS
31
16,15
0
LSB
A0
A1
A2
A3
A4
A5
A6
CONDITION CODE REGISTER
31
16,15
0
A7’ (SSP)
SUPERVISOR STACK POINTER
15
0
8,7
CCR
SR
STATUS REGISTER
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CCR Register
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The Condition Code Register, or CCR register, contains a set of 5
condition bits
- Bits change constantly with the result of each instruction
- X BIT: Extend bit- Used with multi-precision arithmetic
- N BIT: Negative bit- Indicates that the result is a negative number
- Z BIT: Zero bit: Indicates that the result is equal to zero
- V BIT: Overflow: Indicates that the result may have exceeded the
range of the operand
- C BIT: Carry bit: Indicates that a carry was generated in a
mathematical operation
DB7
CCR
DB6
DB5
DB4
X
DB3
DB2
DB1
N
Z
V
DB0
C
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Effective Address
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•
•
The effective address, EA, determines how the operands of an instruction
are to be accessed by the processor
The kinds of EA’s are the addressing modes of the architecture
Consider the form of the opcode word shown below:
MOVE.W
15
•
•
dst EA
12 11
src EA
6
5
0
MOVE.W instruction: Move the word contents of the memory location
specified by the src EA to the memory location specified by the dst EA
- This information is encoded in the 16 bits of the op code word
- OPCODE/SIZE = DB12-DB15
( MOVE.W)
- Source Effective Address = DB0-DB5
- Destination Effective Address = DB6-DB11
May have to retrieve additional words from memory to complete the
instruction
- Note: Not all instructions have the same form as the MOVE instruction
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Instruction format in memory
Example: an immediate operand is the actual data value
- Generally represented as
OP CODE
#DATA
- Example: start
MOVE.W
#$0A55,D0
*Initialize D0
•
EVEN BYTE
7
6
5
15
14
13
4
ODD BYTE
2
1
12 11 10
0
9
8
7
6
7
6
5
5
4
4
3
3
2
2
1
1
OP CODE WORD
FIRST WORD SPECIFIES OPERATIONS AND MODES
0
0
•It is a MOVE.W instruction
• The source operand is immediate data
• The destination operand is register D0
IMMEDIATE OPERAND
IF ANY, ONE OR TWO WORDS
• The immediate data value, $0A55
SOURCE EFFECTIVE ADDRESS EXTENSION
IF ANY, ONE OR TWO WORDS
DESTINATION EFFECTIVE ADDRESS EXTENSION
IF ANY, ONE OR TWO WORDS
Not used
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Instruction format in memory(2)
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Example 2: Absolute operands exactly specify the locations of the data
- Generally represented as: OP CODE source address,dest address
- Example: MOVE.W $0A550000,$1000BB00
EVEN BYTE
7
6
5
15
14
13
4
ODD BYTE
2
1
12 11 10
0
9
8
7
6
7
6
5
5
4
4
3
3
2
2
1
1
OP CODE WORD
FIRST WORD SPECIFIES OPERATIONS AND MODES
SOURCE EFFECTIVE ADDRESS
HIGH ORDER WORD
SOURCE EFFECTIVE ADDRESS
LOW ORDER WORD
DESTINATION EFFECTIVE ADDRESS
HIGH ORDER WORD
DESTINATION EFFECTIVE ADDRESS
LOW ORDER WORD
0
0
•It is a MOVE.W instruction
• The source operand is absolute address
• The destination operand is absolute
address
• $0A55
• $1000
• $0000
• $BB00
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Word Alignment
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•
It is best to try to align memory accesses on natural boundaries
- Some processors (X86) will allow accesses to occur for non-aligned
words
- Requires multiple memory accesses to input data
MC68000 processor does not allow non-aligned accesses
- Will generate an exception trap and an error routine will need to be
called to recover
Low order byte
1
0
3
2
High order byte
•
Trying to address a word beginning at address 1 will cause a non-aligned
access to occur
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Flow charting (3)
Set up
environment
TEST = FALSE
Keyboard
Input
Run Self-tests
TEST = TRUE
8
Scan key board
Interpret
keystroke
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