Transcript ECE Application Programming

16.482 / 16.561
Computer Architecture and
Design
Instructor: Dr. Michael Geiger
Spring 2015
Lecture 8:
Memory hierarchies
Lecture outline

Announcements/reminders

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
HW 6 due today
HW 7 to be posted; due 4/2
Poll posted re: final exam scheduling



Can’t hold 4/30 as originally scheduled
Choices: 4/23 (2nd to last week of classes) or 5/7 (finals week)
2 major questions (in addition to name and explanation of
preference)



Review


Which date(s) are you available?

You are only “unavailable” if you have a legitimate reason for
missing the exam on one of these dates
Which date (if any) do you prefer?
Multiple issue and multithreading
Today’s lecture
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7/21/2015
Memory hierarchies
Computer Architecture Lecture 8
2
Review: TLP, multithreading



ILP (which is implicit) limited on realistic
hardware for single thread of execution
Could look at explicit parallelism: ThreadLevel Parallelism (TLP) or Data-Level
Parallelism (DLP)
Focus on TLP and multithreading
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Coarse-grained: switch threads on a long stall
Fine-grained: switch threads every cycle
Simultaneous: allow multiple threads to execute in
same cycle
Computer Architecture Lecture 8
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Motivating memory hierarchies

Why do we need out-of-order scheduling,
TLP, etc?
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Data dependences cause stalls
The longer it takes to satisfy a dependence, the
longer the stall and the harder we have to work to
find independent instructions to execute
Major source of stall cycles: memory
accesses
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Computer Architecture Lecture 8
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Why care about memory hierarchies?
100,000
Performance
10,000
1,000
Processor-Memory
Performance Gap
Growing
Processor
100
10
Memory
1
1980
1985
1990
1995
2000
2005
2010
Year

Major source of stall cycles: memory accesses
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Computer Architecture Lecture 8
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Motivating memory hierarchies

What characteristics would we like memory to have?

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High capacity
Low latency
Low cost
Can’t satisfy these requirements with one memory
technology
Solution: use a little bit of everything!

Small SRAM array(s)  caches

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Larger DRAM array  main memory or RAM

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Hope you rarely have to use it
Extremely large disk
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Small means fast and cheap
Typically at least 2 levels (often 3) of cache on chip
Costs are decreasing at a faster rate than we fill them
Computer Architecture Lecture 8
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Memory hierarchy analogy
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Looking for something to eat

First step: check the refrigerator
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
Second step: go to the store
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Find item  purchase it, take it home, eat!
Latency = 20-30 minutes
Third step: grow food
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Find item  eat!
Latency = 1 minute
Plant food, wait … wait some more … harvest, eat
Latency = ~250,000 minutes (~6 months)
Computer Architecture Lecture 8
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Terminology


Find data you want at a given level: hit
Data is not present at that level: miss


Hit rate: Fraction of accesses that hit at a
given level

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In this case, check the next lower level
(1 – hit rate) = miss rate
Another performance measure: average
memory access time
AMAT = (hit time) + (miss rate) x (miss penalty)
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Computer Architecture Lecture 8
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Average memory access time
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Given the following:
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Cache: 1 cycle access time
Memory: 100 cycle access time
Disk: 10,000 cycle access time
What is the average memory access time if the
cache hit rate is 90% and the memory hit rate is
80%?
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Computer Architecture Lecture 8
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AMAT example solution
Key point: miss penalty = AMATnext level
 Therefore:
AMAT
= (HT) + (MR)(MP)
= 1 + (0.1)(AMATmemory)
= 1 + (0.1)[100 + (0.2)(AMATdisk)]
= 1 + (0.1)[100 + (0.2)(10,000)]
= 1 + (0.1)[100 + 2000]
= 1 + (0.1)[2100]
= 1 + 210 = 211 cycles
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Computer Architecture Lecture 8
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Memory hierarchy operation

We’d like most accesses to use the cache


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Fastest level of the hierarchy
But, the cache is much smaller than the
address space
Most caches have a hit rate > 80%
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How is that possible?
Cache holds data most likely to be accessed
Computer Architecture Lecture 8
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Principle of locality

Programs don’t access data randomly—they
display locality in two forms
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Temporal locality: if you access a memory
location (e.g., 1000), you are more likely to reaccess that location than some random location
Spatial locality: if you access a memory location
(e.g., 1000), you are more likely to access a
location near it (e.g., 1001) than some random
location
Computer Architecture Lecture 8
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Basic cache design

Each cache line consists of two main parts

Tag: Upper bits of memory address
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Block: Actual data
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Block sizes can vary—typically 32 to 128 bytes
Larger blocks exploit spatial locality
Status bits
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Bits that uniquely identify a given block
Check tag on each access to determine hit or miss
Valid bit: Indicates if line holds valid data
We’ll discuss dirty bit today; other bits in multiprocessors
Valid
Dirty
Tag
Block
1
0
0x1000
0x00
0x12
0x34
0x56
0
0
0x2234
0xAB
0xCD
0x87
0xA9
Computer Architecture Lecture 8
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Cache organization
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Cache consists of multiple tag/block pairs,
called cache lines
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Can search lines in parallel (within reason)
Each line also has a valid bit
Write-back caches have a dirty bit
Note that block sizes can vary
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Most systems use between 32 and 128 bytes
Larger blocks exploit spatial locality
Larger block size  smaller tag size
Computer Architecture Lecture 8
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4 Questions for Memory Hierarchy
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Q1: Where can a block be placed in the upper level?
(Block placement)
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Q2: How is a block found if it is in the upper level?
(Block identification)
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Q3: Which block should be replaced on a miss?
(Block replacement)

Q4: What happens on a write?
(Write strategy)
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Q1: Block placement (cont.)

Three alternatives

Place block anywhere in cache: fully associative


Impractical for anything but very small caches
Place block in a single location: direct mapped
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Line # = (Block #) mod (# lines) = index field of address
Block # = (Address) / (block size)


Place block in a restricted set of locations: set
associative
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In other words, all bits of address except offset
n-way set associative cache has n lines per set
Set # = (Block #) mod (# sets) = index field of address
Computer Architecture Lecture 8
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Block placement example
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Given:
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A cache with 16 lines numbered 0-15
Main memory that holds 2048 blocks of the same
size as each cache block
Determine which cache line(s) will be used
for each of the memory blocks below, if the
cache is (i) direct-mapped, or (ii) 4-way set
associative
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Block 0
Block 13
Block 249
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Solution
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Cache line # = (block #) mod (# sets)

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“mod” = remainder of division (e.g., 5 mod 3 = 2)
Direct-mapped cache: 1 line per “set”
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Block 0  line (0 mod 16) = 0
Block 13  line (13 mod 16) = 13
Block 249  line (249 mod 16) = 9
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4-way SA cache: 4 lines per set  4 total sets
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249 / 16 = 15 R9
Block 0  set (0 mod 4) = lines 0-3
Block 13  set (13 mod 4) = set 1 = lines 4-7
Block 249  set (249 mod 4) = set 1 = lines 4-7
Computer Architecture Lecture 8
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Q2: Block identification
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Tag on each block
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No need to check index or block offset
Increasing associativity shrinks index,
expands tag
Block Address
Tag
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Index
Computer Architecture Lecture 8
Block
Offset
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Address breakdown
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Can address single byte (smallest addressable unit)
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Block offset: byte address within block
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If addressing multiple bytes, address is lowest in word/half-word
E.g., word containing bytes 0-3 accessed by address 0
# block offset bits = log2(block size)
Index: line (or set) number within cache

# index bits = log2(# of cache lines or sets)
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# of cache sets =
total cache size
(block size)  (associativity)

Tag: remaining bits
Tag
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Index
Computer Architecture Lecture 8
Block
offset
20
Mapping memory to cache
Example:
 8-byte cache
 2-byte blocks
 16-byte
memory
tag data
0
1
2
3
Address:
tag
1 bit
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index
block offset
2 bits
1 bit
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1
2
3
4
5
6
7
8
9
10
11
12
13
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15
78
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120
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71
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162
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18
21
33
28
19
200
210
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Mapping memory example

Say we have the following cache organization
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Direct-mapped
4-byte blocks
32 B cache
6-bit memory addresses
Given the addresses below, answer the following
questions

Which addresses belong to the exact same block?
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Which addresses map to the same cache line, but are part
of different blocks?
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i.e., both tag and index are equal
i.e., index numbers are equal, but tags are different
Addresses: 3, 4, 6, 11, 37, 43
Computer Architecture Lecture 8
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Solution
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Figure out size of each field
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4 = 22 bytes per block
 2-bit offset
32 / (4 x 1) = 8 = 23 cache
lines  3-bit index
6-bit address, 5 bits for
offset & index  1-bit tag
Convert addresses into
binary
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3 = 0 000 11
4 = 0 001 00
6 = 0 001 10
11 = 0 010 11
37 = 1 001 01
43 = 1 010 11

Addresses 4 & 6 are part of
same block

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Address 37 maps to same
cache line as 4 & 6, but
different block

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Index = 001, tag = 0
Index = 001, tag = 1
Addresses 11 & 43 map to
same cache line, but
different blocks

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Index = 010 for both
Tag = 0 for 11, 1 for 43
Computer Architecture Lecture 8
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Q3: Block replacement

On cache miss, bring requested data into
cache

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If line contains valid data, that data is evicted
When we need to evict a line, what do we
choose?

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Easy choice for direct-mapped—only one
possibility!
For set-associative or fully-associative, choose
least recently used (LRU) line
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Want to choose data that is least likely to be used next
Temporal locality suggests that’s the line that was
accessed farthest in the past
Computer Architecture Lecture 8
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Direct-mapped cache example

Assume the following simple setup
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Only 2 levels to hierarchy
16-byte memory  4-bit addresses
Cache organization

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
Leads to the following address breakdown:
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Direct-mapped
8 total bytes
2 bytes per block  4 lines
Write-back cache
Offset: 1 bit
Index: 2 bits
Tag: 1 bit
Computer Architecture Lecture 8
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Direct-mapped example (cont.)

We’ll use the following sequence of accesses
lb
lb
sb
sb
lb
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$t0,
$t1,
$t1,
$t0,
$t1,
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
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Direct-mapped cache example: initial state
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = ?, $t1 = ?
Cache
78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
V
D
Tag
0
0
0
0
0
0
0
0
0
0
12
19
0
0
0
0
0
13
200
0
0
0
0
0
14
210
15
225
7/21/2015
Data
0
Computer Architecture Lecture 8
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Direct-mapped cache example: access #1
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 1 = 00012
 Tag = 0
 Index = 00
 Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = ?, $t1 = ?
Cache
V
D
Tag
0
0
0
Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7/21/2015
Hits: 0
Misses: 0
Computer Architecture Lecture 8
0
78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
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Direct-mapped cache example: access #1
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 1 = 00012
 Tag = 0
 Index = 00
 Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = ?
Cache
V
D
Tag
1
0
0
78
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Data
Hits: 0
Misses: 1
Computer Architecture Lecture 8
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78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
29
Direct-mapped cache example: access #2
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 8 = 10002
 Tag = 1
 Index = 00
 Offset = 0
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = ?
Cache
V
D
Tag
1
0
0
Data
78
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7/21/2015
Hits: 0
Misses: 1
Computer Architecture Lecture 8
0
78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
30
Direct-mapped cache example: access #2
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 8 = 10002
Tag = 1
Index = 00
Offset = 0
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7/21/2015
Hits: 0
Misses: 2
Computer Architecture Lecture 8
0
78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
31
Direct-mapped cache example: access #3
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 4 = 01002
 Tag = 0
 Index = 10
 Offset = 0
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Hits: 0
Misses: 2
Computer Architecture Lecture 8
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78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
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Q4: What happens on a write?
Write-Through
Write-Back
Write data only
to the cache
Policy
Data written to
cache block
also written to
lower-level
memory
Update lower
level when a
block falls out of
the cache
Debug
Easy
Hard
Do read misses
produce writes?
No
Yes
Do repeated
writes make it
to lower level?
Yes
No
7/21/2015
Computer Architecture Lecture 8
33
Write policy example

Say we have the following code sequence:
lw
addi
sw
addi
sw
addi
sw


$t0,
$t2,
$t2,
$t2,
$t2,
$t2,
$t2,
0($t1)
$t0, 5
4($t1)
$t2, 10
8($t1)
$t2, 20
12($t1)
Assume all addresses map to the same cache block
Assume this initial cache line state (each block entry is 1 word,
not 1 byte, shown in decimal)
Valid
Dirty
Tag
Block
1
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0
1000
100
Computer Architecture Lecture 8
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0
0
34
Write policy example (cont.)


In write-through cache, no need for dirty bit
Every single write (store instruction) causes entire
block to be written to memory



7/21/2015
After first store, cache line:
Valid
Tag
1
1000
Block
100
105
0
0
115
0
After second store:
Valid
Tag
1
1000
Block
100
105
After third store
Valid
Tag
1
1000
Block
100
105
Computer Architecture Lecture 8
115
135
35
Write policy example (cont.)


Write-through cache produces 3 memory writes
 Not strictly necessary—as long as data remains in cache, most
up-to-date value is available at top of hierarchy
 Accesses never go to memory until block is evicted
In write-back cache, only write data to memory on eviction
 Check dirty bit to see if write back is needed



Bit is set on every write to block
Bit is cleared when block is evicted and new data brought into line
After first store:
Valid
Dirty
1


7/21/2015
1
Tag
1000
Block
100
105
0
0
Second, third store proceed in same way
Difference is that no writes to memory occur in this sequence!
Computer Architecture Lecture 8
36
Direct-mapped cache example: access #3
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 4 = 01002
 Tag = 0
 Index = 10
 Offset = 0
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
0
18
150
0
0
0
0
0
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Hits: 0
Misses: 3
Computer Architecture Lecture 8
0
78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
37
Direct-mapped cache example: access #4
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 13 = 11012
 Tag = 1
 Index = 10
 Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
0
18
150
0
0
0
0
0
7/21/2015
Hits: 0
Misses: 3
Computer Architecture Lecture 8
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78
1
29
2
120
3
123
4
71
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
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200
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210
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Direct-mapped cache example: access #4
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 13 = 11012
Tag = 1
Index = 10
Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Must write back
dirty block
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
0
18
150
0
0
0
0
0
7/21/2015
Hits: 0
Misses: 4
Computer Architecture Lecture 8
0
78
1
29
2
120
3
123
4
18
5
150
6
162
7
173
8
18
9
21
10
33
11
28
12
19
13
200
14
210
15
225
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Direct-mapped cache example: access #4
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 13 = 11012
Tag = 1
Index = 10
Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
1
19
29
0
0
0
0
0
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Hits: 0
Misses: 4
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Direct-mapped cache example: access #5
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 9 = 10012
 Tag = 1
 Index = 00
 Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
1
19
29
0
0
0
0
0
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Misses: 4
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Direct-mapped cache example: access #5
Instructions:
lb
lb
sb
sb
lb
$t0,
$t1,
$t1,
$t0,
$t1,
Memory
Address = 9 = 10012
 Tag = 1
 Index = 00
 Offset = 1
1($zero)
8($zero)
4($zero)
13($zero)
9($zero)
Registers:
$t0 = 29, $t1 = 21
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
1
19
29
0
0
0
0
0
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Additional examples

Given the final cache state above, determine
the new cache state after the following three
accesses:



7/21/2015
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t0, 11($zero)
Computer Architecture Lecture 8
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Direct-mapped cache example: access #6
Memory
Instructions:
Address = 3 = 00112
 Tag = 0
 Index = 01
 Offset = 1
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 18
Cache
V
D
Tag
1
0
1
Data
18
21
0
0
0
0
0
1
1
1
19
29
0
0
0
0
0
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Hits: 1
Misses: 4
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Direct-mapped cache example: access #6
Memory
Instructions:
Address = 3 = 00112
 Tag = 0
 Index = 01
 Offset = 1
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 123
Cache
V
D
Tag
1
0
1
Data
18
21
1
0
0
120
123
1
1
1
19
29
0
0
0
0
0
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Hits: 1
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Direct-mapped cache example: access #7
Memory
Instructions:
Address = 2 = 00102
 Tag = 0
 Index = 01
 Offset = 0
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 123
Cache
V
D
Tag
1
0
1
Data
18
21
1
0
0
120
123
1
1
1
19
29
0
0
0
0
0
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Hits: 1
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Direct-mapped cache example: access #7
Memory
Instructions:
Address = 2 = 00102
 Tag = 0
 Index = 01
 Offset = 0
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 123
Cache
V
D
Tag
1
0
1
Data
18
21
1
1
0
29
123
1
1
1
19
29
0
0
0
0
0
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Hits: 2
Misses: 5
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Direct-mapped cache example: access #8
Memory
Instructions:
Address = 11 = 10112
 Tag = 1
 Index = 01
 Offset = 1
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 123
Cache
V
D
Tag
1
0
1
Data
18
21
1
1
0
29
123
1
1
1
19
29
0
0
0
0
0
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Hits: 2
Misses: 5
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Direct-mapped cache example: access #8
Memory
Instructions:
Address = 11 = 10112
 Tag = 1
 Index = 01
 Offset = 1
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Must write back
dirty block
Registers:
$t0 = 29, $t1 = 123
Cache
V
D
Tag
1
0
1
Data
18
21
1
1
0
29
123
1
1
1
19
29
0
0
0
0
0
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Hits: 2
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Direct-mapped cache example: access #8
Memory
Instructions:
Address = 11 = 10112
 Tag = 1
 Index = 01
 Offset = 1
lb $t1, 3($zero)
sb $t0, 2($zero)
lb $t1, 11($zero)
Registers:
$t0 = 29, $t1 = 28
Cache
V
D
Tag
1
0
1
Data
18
21
1
0
1
33
28
1
1
1
19
29
0
0
0
0
0
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Hits: 2
Misses: 6
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Final notes

Next time




Set associative caches
Cache optimizations
Virtual memory
Reminders



HW 6 due today
HW 7 to be posted; due 4/2
Poll posted re: final exam scheduling



Can’t hold 4/30 as originally scheduled
Choices: 4/23 (2nd to last week of classes) or 5/7 (finals week)
2 major questions (in addition to name and explanation of
preference)


7/21/2015
Which date(s) are you available?

You are only “unavailable” if you have a legitimate reason for
missing the exam on one of these dates
Which date (if any) do you prefer?
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