Transcript Achieving Non-Inclusive Cache Performance Without Non

JILP
2nd JILP Workshop on
Computer Architecture Competitions (JWAC-2):
Championship Branch Prediction
Sponsored by JILP and Intel’s Academic Research Office
JILP
Submissions
• Two tracks
– Conditional branch predictor
– Indirect branch predictor
• Submissions
– 11 total papers ( 7 conditional, 4 indirect)
• Distribution
– Asia – 2
– Europe - 2
– North America - 7
JILP
Metrics
• Performance Ranking
• Novel Ideas
• Overall Paper Quality
• Adherence to Competition Rules
JILP
Process
• Reviews
– 2 to 3 reviews per paper
• Offline program committee meeting
9 Papers Accepted
JILP
Types of Algorithms/Enhancements
• Base algorithms:
•
•
•
•
•
TAGE and ITTAGE
OGEHL
Perceptron predictor
Neural Analog predictor
Loop predictor
• Enhancements
•
•
•
•
•
Immediate update mimicker
Adaptive Rehashing
Misprediction penalty
Load-branch correlation
Many more: target compression, dynamic fitting, filters etc.
5
JILP
• Organizing Committee
– Hongliang Gao, Intel (Chair)
– Alaa Alameldeen, Intel
– Chris Wilkerson, Intel
• Web
– Eric Rottenberg
Thanks
• Program Committee
– Trevor Mudge, University of
Michigan (Chair)
– Alaa Alameldeen, Intel
– Hongliang Gao, Intel
– Daniel Jimenez, UT-San Antonio
– Yale Patt, Texas
– Andre Seznec, INRIA
– Lucian Vintan, University of Sibiu
– Chris Wilkerson, Intel
Sponsors:
•Intel’s Academic Research Office
•JILP