Esperimento LHCb - Istituto Nazionale di Fisica Nucleare
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Transcript Esperimento LHCb - Istituto Nazionale di Fisica Nucleare
The L0 Calorimeter Trigger
U. Marconi
On behalf of the Bologna Group
CSN1, Catania 16/9/02
Calorimeter
Trigger
INFN Sezione di Bologna
LHCb Trigger Performances
L1 Trigger
using
L0 information
INFN Sezione di Bologna
L0 Calorimeter Trigger – L1 Trigger
L1-Trigger
With
pT info
INFN Sezione di Bologna
Calorimeter Trigger Basic Principles
Identify hot spots
Detect a high energy in a small surface
Use a square of 2 x 2 cells area
8 x 8 cm2 in the central region of ECAL (may loose a few % of
the energy)
more than 50 x 50 cm2 in the outer region of HCAL
Select the particles with the highest ET
Due to its high mass, a B particle decays into high PT
particles
'High PT ' is a few GeV
For the Level 0 decision, we need the particle with the highest
PT (the second highest also in HCAL)
INFN Sezione di Bologna
Select locally the highest candidate (reducing
complexity and cabling)
Process further only the local candidates
~200 for ECAL and ~50 for HCAL starting from 6000
and 1500 cells.
Validate the candidates
Electron, photon, 0:
Electromagnetic nature using the PreShower
Charge using the SPD
Hadron
Add the energy lost in ECAL in front of the HCAL
candidate, looking only at ECAL candidates (manageable
number of connections)
INFN Sezione di Bologna
Select the highest validated candidates
One wants the highest ET candidates
Ghosts removal
Second highest for hadrons
No need for a second highest for electron or
photon.
The processing is entirely synchronous
No dependence on occupancy and history
Easier to understand and to debug
Pipeline processing at all stages.
INFN Sezione di Bologna
HCAL
ECAL
PreShower / SPD
Detector + PM
8x4 cells/FE card
10 m cables
F
E
F
E
F
E
Address
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
F
E
80 links
from 50 cards
8 inputs
SPD
multiplicity
LUT
address match
LUT
Add
highest
highest
local
global
4 outputs
16 inputs
28 inputs
28 inputs
28 inputs
14 ECAL crates
4 HCAL cartes
8 Prs/SPD crates
8 cards per half
crate
One Validation card
per half ECAL crate
One SPD sum per
half PreShower crate
highest
highest
photon
F
E
LVDS links
E TOT
highest
electron
F
E
4 inputs
8 inputs
8 inputs x 8 bits
F
E
28 inputs
Platform on top of calorimeter
F
E
Validation Card
80 m optical link
80 inputs
Merge back to 50
Selection Crate
Add
Highest
Electron
Highest
Photon
Highest
local
Highest
global
Highest
Hadron
Level 0 Decision Unit
INFN Sezione di Bologna
Second
Highest
Total
Energy
LVDS links
L0 Decision Unit
Barrack
SPD
multiplicity
Hardware Implementation
About 6000 ECAL cells (as well as for the PreShower
and the SPD)
Variable cell size, identical structure for
SPD/PreShower /ECAL
Front-end electronics located on top of the detector
Use SEU immune components (order of 100 rads/year)
32 channels per FE card for ECAL/HCAL, 64 for Prs/SPD
Minimal cabling complexity
HCAL different, see later
Use a dedicated backplane for as many connections as possible
8 bits ET converted from the 12 bits ADC.
8 bits are adeguate with a full scale limit around 5 GeV.
INFN Sezione di Bologna
First selection
Build the 2x2 sums
Work inside a 32 channels (8x4) front-end card
To obtain the 32 2x2 sums, one needs to get the 8 + 1 + 4
neighbours
Via the backplane (9) or dedicated point-to-point
cables(4)
Neighbours
of each cell
: 8 bits LVDS multiplexed link
: 8 bits on the backplane
INFN Sezione di Bologna
Block diagram of the Front_End Board (LAL-ORSAY)
LEds
Channel 7 32
15
23
31
Test Seq
Test
Ram
256
Trigger Data
32 Channels
from Pms
Shaper
Adaptation
Delay lines
ADC
12 bits/
40Mhz
Low
Frequency
noise
rejection
Neighbours
top& bottom
Serializer
21/4
21
To Validation
L0
Lattency
Ram
Trigger
Spy Fifo
FE_Pga
Specs
ExtChannel 12..4
72
Specs
L0 Data
Timing Adjustment
Setup
Delay lines
20
Side
neighbours
Test Seq
Specs
LVTTL
Seq_Pga
Analog Input
connectors
16
Deserializer
ExtChannel 3
21/4
16
2 32
1
0
clk4lvdsRv
clkfromTopRv
Max
Cluster
Specs
Serializer
21/4
Sequencer
Event
Builder
Event
Formater
Channel 7..0
72
L0
L1
Specs
To Croc
Serializer
21/4
L1
Fifo
Specs
Jtag
Serial link
Common
Backplane
Specs Slave
Power
Supplies
Clock
Version 1/07/2002
INFN Sezione di Bologna
14
14
12
16
4
5 6 7 8
9 10 11 12
13 14
Crates 1 and 2
1 2 3 4
5 6 7 8
9 10 11 12
13 14 15 16
Crate 3
3 4
5 6 7 8
9 10 11 12
13 14 15 16
Crates 4 and 5
3 4
5 6 7 8
9 10 11 12
13 14
Crate 6
9 10 11 12
13 14
Crate 7
2 3
1
13
13
11
12
12
10
14
11
11
9
13
10
10
9
9
8
7
2
8
7
15
3
12
12
14
16
11
11
10
10
9
9
15
14
13
12
8
47
8
6
6
5
5
4
5 43
13
11
10
9
8
77
6
5
4
3
14
7
14
13
12
11
10
9
68
7
6
4
5
64
3
16
6
6
5
5
4
8
4
4
3
7
3
3
13
15
No neighbours
3 4
3
3
2
6
2
2
1
5
5 6 7 8
Validation
Card
ECAL
Left
INFN Sezione di Bologna
CROC
Validation
Card
INFN Sezione di Bologna
ECAL Validation
For each ECAL candidate, one needs to access
the SPD and the PreShower information (2
times 4 bits for the SPD&Preshower cells
corresponding to the ECAL candidate)
The address is sent from the ECAL to the
PreShower FE bords
One PreShower board handles 64 channels
(exactly 2 ECAL boards)
The 24 bits are extracted synchronously at
each BX and sent to the Validation Card
INFN Sezione di Bologna
ECAL Validation produces 4 candidate types
Electrons and photons are validated FE-candidates
‘local 0’ is detected as a high total energy on a card
‘global 0’ is detected by summing the energies of two FEcandidates of two adjacent cards.
No SPD/PreShower validation foreseen for the 0, but this will
be integrated in the card, in case…
Only the highest Et ECAL candidate is interesting
This is just a few more output bits of the previous LUT, plus the
validation of a register.
We select the highest of the 8 on the Validation card
Output 4 ECAL candidates
Each has 8 bits Et and 8 bits address, plus BX-ID.
INFN Sezione di Bologna
HCAL Validation
Ideal case: Add the ECAL cells in front of the HCAL
candidate, but this implies a lot of connections, at 40
MHz.
This addition is important only if the ECAL energy
deposit is large, then likely, it also has a large chance
to be detected as a local maximum in the ECAL FEboard.
Send the 50 HCAL candidates to the ECAL ones
Less connections, some duplication, but we can use the ECAL
Validation Card.
One ECAL FE-board matches only one HCAL card.
One validation card receives at most four HCAL cards
One HCAL card goes at most (30 of 50) to two Validation
cards
INFN Sezione di Bologna
Validation board
LEds
Etrans3-2Hcal_Pga < 150 IO
24 AddMatch 7:0
3 AddMatch 7
3
3V dec
Hcal3 Sel
Etrans3
8
5
64
8 Hcal 3 Et 7:0
Hcal Sel 7:0
20
Mux
Hcal 3:0 add 4:0
Deserializer
21/4
52
Mux
3
5
I2C int
Address
Match
Hcalsel7
3Vreg
5
Ecal Add 0
pipeline(hcal logic)
20
LUT
1K8
Hcal add
Hcal 2 logic
Specs
Etrans1
From local
Fe Ecal
8
5
Hcal 1 add
Ecal7Etclus7:0
Ecal7 eval
Highest Etrans
8
electron
8
5
Max
Comp
in cascade
Ecal0Etclus7:0 3V dec
Ecal 0eval
Etrans1-0 Hcal_Pga
Hcal 0 add
48
PS/SPD7
e/p valid
8 PS/SPD7 val 7:0
Monitoring
Fifo
Highest electron
Highest photon
E,P,Pi,GloPi,HcalClust
101
Global
Pi0
PS/SPD7
e/p valid
Global Pi0
PS/SPD7
e/p valid
Ecal0Etclus7:0
Ecal 0eval
8
Ecal 7:0 add 4:0
64
Ecal 7:0 Etclus7:0
Ecal7Etclus7:0
Max
Comp
in cascade
pival6
pival0
PS/SPD7
e/p valid
8
48
PS/SPD7
e/p valid
Ecal0Etclus7:0
Ecal 0eval
From
PS/SPD crates
PS/SPD7:0 val 7:0 Deserializer
PS/SPD7:0 add 5:0 21/4
168
Ecal1Etclus
Ecal0Etclus
Ecal7 eval
Max
Comp
in cascade
PS/SPD0 val 7:0
40
42
Local Pi0
8
LUT
1K8
+ Ecal6Etclus7:0
8
8 PS/SPD7 val 7:0
LUT
1K8
Pi0_Pga
Max
Comp
in cascade
8
Specs
8
Ecal7Etclus7:0
Ecal7 eval
8
32
168
LUT
1K8
add 8
Highest
photon
8
PS/SPD7 val 7:0
LUT
1K8
PS/SPD7
e/p valid
8
PS/SPD0 val 7:0
LUT
1K8
8 PS/SPD0 val 7:0
LUT
1K8
3
64
Ecal 7:0 EtSum7:0
not decided yet
Jtag
Serial link
Common
Backplane
Specs Slave
Power
Supplies
Clock
Version 1/07/2002
INFN Sezione di Bologna
PCI
Connector
Ecal 7:0 Etclus7:0
Ecal 7:0 Ettot 7:0
Ecal 7:0 Clustadd4:0 Deserializer
21/4
-
e phot pi_Pga
Etrans0
GLink Interface
RJ45
From
Hcal Crates
Hcalsel0
Hcal 3:0 add 4:0
Hcal 3:0 Et 7:0
Hcal 3 logic
5
5
2
LUT
1K8
Ecal 7:0Et 7:0
Ecal Et 7
Hcal 2 add
Mux_Pga
8 Hcal 3:2 Et 7:0
Hcal Sel 0
Ecal Et 0
AddMatch 0
Sum
8
40
16
8
Hcal3add
Etrans2
Hcal Add 7:0
5 Ecal Add 7
decode
Max
Comp
5
Address
Match
16 Hcal Sel
2 Hcal Sel 7
8
GLink Interface
LAL ORSAY
RJ45
The Optical Links
The Optical Links are used to transmit the
calorimeter-clusters from the Validation
Cards to the Selection Crate
The total amount of the optical channels
16 (SPD) + 428 (ECAL) + 80 (HCAL) = 208 Ch
Cluster bit patterns
HCAL: 8 bits (BX) + 8 bits (ET) + 5 bits (Address)
ECAL: 8 bits (BX) + 8 bits (ET) + 8 bits (Address)
SPD: 8 bits (BX) + 10 bits (Mult.)
INFN Sezione di Bologna
Optical Link. Tx/Rx Prototypes
Optical Tx
32-bits
Data Input
PLD
Clock
G-Link
Serial Protocol
Power Consumption
2.5W Rx
INFN Sezione di Bologna
Optical
Tx/Rx
Optical Tx/Rx.
Bit Error Rate Measurements
Clock Jitter Characteristics
External Clock
Bit-Pattern and
Pick-to-pick: 220 ps
: 34.2 ps
Control-bits
Generator
INFN Sezione di Bologna
To the Optical Rx
Optical Tx/Rx. Test Setup
VME
Pattern Unit
Control-Board
Optical Channel
Tx/Rx
Overall Latency
500 ns
Tx: 1 clock cycle
Rx: 3 clock cycles
Recovery Time
~1ms
INFN Sezione di Bologna
BER vs Jitter Glink Optical Channel
Jitter Modulation
BER vs Jitter
Jitter (ps)
1,00E-04
1,00E-06
1,00E-08
1,00E-10
120
100
80
60
40
1,00E-12
1,00E-14
1,00E-16
20
54,8
Ext. Modulation
33120 Agilent
Noise Generator
59,2
61,2
68
75,1
Jitter (ps)
Ext. Trigger Sine Wave 40MHz
50
24
50
21
50
18
50
15
50
12
0
95
0
65
0
50
0
34,2
Vpp(mV)
140
35
BER
1,00E+00
1,00E-02
Vpp Noise[mV]
Clock with jitter
PMT5193
PG9210
LC584
40.00 MHz
Philips PM5193
Le Croy PG9210
Function Generator
Pulse Generator
And Modulator
INFN Sezione di Bologna
Le Croy LC584
Oscilloscope
TRANSMIT
32 bits @ 40 MHz
Data in
Clock
GOL
(Gigabit Optical Link)
Optical
Transmitter
(FTRJ-8519-1-2.5)
Optical
40 MHz
RECEIVE
32 bits @ 40 MHz
Fibre
16 bits @ 80 MHz
Power Consumption
360mW
1.2 Gb/s
Data out
Demultiplexer
Optical
Receiver
TLK2501
(FTRJ-8519-1-2.5)
Clock
40 MHz
Max peak-to-peak
Jitter 40ps
INFN Sezione di Bologna
L9
VDDT X
C1 6 0
C1 6 1
10 0n F 10 nF
10 nF
C1 5 9
HZ 0 8 0 5 E 6 0 1 R- 0 0
C1 6 2
L1 0
VCCT X
VDD2 .5 A TX
C1 6 3
10 0n F 10 nF
VCCT TX
C1 6 7
C1 6 5 HZ 0 8 0 5 E 6 0 1 R- 0 0
C1 6 6
10 nF
10 0n F 10 nF
C1 6 4
d i n [3 1 ..0 ]
4 . 7 µF 1 0 V 0 8 0 5
HZ 0 8 0 5 E 6 0 1 R- 0 0
C1 5 8
10 nF
VDD2 .5 T X
4 . 7 µF 1 0 V 0 8 0 5
L8
VDDT X
C1 6 8
C1 6 9
A1
A2
A1 1
A1 2
B1
B2
B1 1
B1 2
C7
C8
C9
D5
D6
E4
E1 0
F4
F9
G9
H4
H1 0
J5
J6
J7
J8
J9
L1
L2
L1 1
L1 2
M1
M2
M1 1
M1 2
J1 4
1
2
D1
10 nF
J3
re a d y
51
c l k L HC
c l k L HCp
c l k L HCn
J2
te s t_ a n a l o g F2
te s t_ s h i ft
te s t_ a n a l o g
te s t_ s h i ft 51
c o n f_ g l i n k
C2
c o n f_ g l i n k D1 2 c o n f_ n e g e d g e
c o n f_ n e g e d g eE2
c o n f_ wm o d e 1 6
c o n f_ wm o d e 1 6
s e l e c tDi ff
GND
GND
SW 3
i 2 c _ a d d r6
i 2 c _ a d d r5
i 2 c _ a d d r4
i 2 c _ a d d r3
i 2 c _ a d d r2
i 2 c _ a d d r1
te s t_ s h i ft
s e l e c tDi ff
J1 0
2
4
R1 2 6
R1 2 8
VDDT X
1
3
HE ADER2 x 2
R1 3 2
330
SW DIP-8 /SM
J1 1
fl a g 0
fl a g 1
FF
4. 7K
RR2
VDD2 .5 T X
R1 3 9
1
2
4. 7K
RR3
VDD2 .5 T X
D5
LED
J1 2
R1 4 1
2
1
1
2
3
4
5
6
7
8
9
SDA
51
SCL
i 2 c _ a d d r651
i 2 c _ a d d r5
i 2 c _ a d d r4
i 2 c _ a d d r3
i 2 c _ a d d r2
i 2 c _ a d d r1
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
VDD2 .5 T X
K4
SDA K3
SCL D3
i 2 c _ a d d r<6 >C3
i 2 c _ a d d r<5 >C4
i 2 c _ a d d r<4 >A4
i 2 c _ a d d r<3 >A5
i 2 c _ a d d r<2 >B5
i 2 c _ a d d r<1 >
F1 0
fl a g < 0 > E1 2
fl a g < 1 > E1 1
FF
J9
R1 1 6
J T AGTCK
J T AGTDO
J T AGTDI
J T AGTM S
J T AGTRS T_ b
SW 4
3
da v
ca v
E1
J T AGTCK G3
J T AGTDO H1
J T AGTDI G1
J T AGTM S J 1
J T AGTRS T_ b
FT RJ -8 5 1 9 - 1 -2 -5
HE ADER2
GOL
SD
c o n f_ i _ p l l
7
1
C1 7 1
B4
3
c o n f_ i _ l d 0
c o n f_ i _ l d 1
c o n f_ i _ l a s e r
HE ADER7
re a d y
R1 0 7
49.9 1% 0402
A8
5
4
1
2.2K
Q2
M M B T2 3 6 9 A
c o n f_ i _ l d 0
c o n f_ i _ l d 1
c o n f_ i _ l a s e r
c o n f_ i _ p l l
fl a g 0
fl a g 1
FF
HE ADER2
re s e t _ b
SW DIP-8 /SM
4. 7K
RR4
VDD2 .5 T X
SW 5
c o n f_ g l i n k
c o n f_ n e g e d g e
c o n f_ wm o d e 1 6
da v
ca v
SW DIP-8 /SM
SW 6
R1 4 5
10K
VCC
MR
RE SE T
re s e t TX
2
GND
GOL Tx Scheme
U1 0
3
4
VDDT X
M AX6 3 1 5
1
R1 4 4
49.9 1%
re s e t TX
c o n f_ i _ p l l
RX +
RX -
TX +
TX -
10 nF
PUSHBUT TON
LEM O
HE ADER2
100
Id _ c a th o d e
9
10
VDD2 .5 A TX
A6
s e ri a l _ l i n e _ p
G4
c o n f_ i _ I d <0 >H2
c o n f_ i _ I d <1 >D2
c o n f_ i _ l a s e r
U9
C1 7 0
A7
s e ri a l _ l i n e _ n
2
TDIS
1
2
3
4
5
6
7
8
9
R1 4 3
J1 3
d i n <0 >
d i n <1 >
d i n <2 >
d i n <3 >
d i n <4 >
d i n <5 >
d i n <6 >
d i n <7 >
d i n <8 >
d i n <9 >
d i n <1 0 >
d i n <1 1 >
d i n <1 2 >
d i n <1 3 >
d i n <1 4 >
d i n <1 5 >
d i n <1 6 >
d i n <1 7 >
d i n <1 8 >
d i n <1 9 >
d i n <2 0 >
d i n <2 1 >
d i n <2 2 >
d i n <2 3 >
d i n <2 4 >
d i n <2 5 >
d i n <2 6 >
d i n <2 7 >
d i n <2 8 >
d i n <2 9 >
d i n <3 0 >
d i n <3 1 >
VCCT VCCR
2
D1 0
C1 2
D1 1
s e l e c tDi ffC1 1
C1 7 2
10 nF
L3
R1 0 2 L 4
R1 0 3 L 5
R1 0 4 M 5
R1 0 5 M 6
R1 0 6 L 7
R1 0 8 M 8
R1 0 9 M 9
R1 1 0 L 9
R1 1 1 K9
R1 1 2 K1 0
R1 1 3 J 1 0
R1 1 4 J 1 1
R1 1 5 H1 1
R1 1 7 G1 1
R1 1 8 F1 2
R1 1 9 K5
R1 2 0 M 4
R1 2 1 K6
R1 2 2 L 6
R1 2 3 M 7
R1 2 4 K7
R1 2 5 L 8
R1 2 7 K8
R1 2 9 M 1 0
R1 3 0 L 1 0
R1 3 1 K1 1
R1 3 3 K1 2
R1 3 4 J 1 2
R1 3 5 H1 2
R1 3 6 G1 2
R1 3 7 F1 1
R1 3 8
da v
F1
ca v
G2
R1 4 0
51
R1 4 2
open
VDD2 .5 T X
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
8
GND T p
GND T p
GND T P
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
GND T p
4
8
12
16
20
24
28
32
36
40
44
48
di n0
di n1
di n2
di n3
di n4
di n5
di n6
di n7
di n8
di n9
di n10
di n11
di n12
di n13
di n14
di n15
di n16
di n17
di n18
di n19
di n20
di n21
di n22
di n23
di n24
di n25
di n26
di n27
di n28
di n29
di n30
di n31
M e tri c a l 4 x 1 2
VDD2 .5 T X
R1 0 1
49.9 1% 0402
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
HE ADER2 x 3 2
a1
b1
c1
a2
b2
c2
a 3 a1 b1 c1 d1
b 3 a2 b2 c2 d2
c 3 a3 b3 c3 d3
a 4 a4 b4 c4 d4
b 4 a5 b5 c5 d5
c 4 a6 b6 c6 d6
a 5 a7 b7 c7 d7
b 5 a8 b8 c8 d8
c 5 a9 b9 c9 d9
a 6 a10 b10 c10 d10
b 6 a11 b11 c11 d11
c 6 a12 b12 c12 d12
Dis posiz ione
a 7 del
le fi le.
b 7 Lat o TOP
c7
a8
b8
c8
d1
a9
d2
b9
d3
c9
d4
a1 0
d5
b1 0
d6
c1 0
d7
a1 1
d8
b1 1
d9
c1 1
d1 0
a1 2
d1 1
b1 2
d1 2
c1 2
6
10 nF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
2
3
5
6
7
9
10
11
13
14
15
17
18
19
21
22
23
25
26
27
29
30
31
33
34
35
37
38
39
41
42
43
45
46
47
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
di n0
di n1
di n2
di n3
di n4
di n5
di n6
di n7
di n8
di n9
di n10
di n11
di n12
di n13
di n14
di n15
di n16
di n17
di n18
di n19
di n20
di n21
di n22
di n23
di n24
di n25
di n26
di n27
di n28
di n29
di n30
di n31
re a d y
SDA
SCL
di n0
di n1
di n2
di n3
di n4
di n5
di n6
di n7
di n8
di n9
di n10
di n11
di n12
di n13
di n14
di n15
di n16
di n17
di n18
di n19
di n20
di n21
di n22
di n23
di n24
di n25
di n26
di n27
di n28
di n29
di n30
di n31
A3
A9
A1 0
B3
B6
B7
B8
B9
B1 0
C1
C1 0
C5
C6
D4
D7
D8
D9
E3
E9
F3
G1 0
H3
H9
J4
K1
K2
M3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
U8
VCCT TX
VDD2 .5 T X
CON2
J8
Ing. Ignazio Lax
I.N.F.N. Electronic Group - Bologna
Ti tl e
TX GOL
INFN Sezione di Bologna
Si z e
A3
Do c u m e n t Nu m b e r
Da te :
W edn es day , J uly 31, 20 02
Optical Link TX RX 3.2
Sh e e t
Re v
0
LHCB
3
of
3
Jitter Filter by PLL
The best Jitter
Jitter at the PLL output
40
we can achieve now
~16ps rms
35
PLL Jitter (ps)
30
25
20
15
LC584
10
5
0
0
20
40
60
80
100
120
Jitter (ps)
33120 Agilent
Noise Generator
Vpp(mV)
Le Croy LC584
Oscilloscope
PMT5193
PG9210
ITD5993A
40.00 MHz
Philips PM5193
Le Croy PG9210
Function Generator
Pulse Generator
And Modulator
INFN Sezione di Bologna
ITD 5993 PLL Filter
The Selection Crate
The 4 ECAL types are processed the same way
The complete cluster-address assignement is performed
The highest of the 28 inputs for each cluster type is
selected and sent to the L0DU
The HCAL processing
Cluster copies are removed, the highest is selected
The complete cluster-address is produced
Ghosts are removed
Cluster selection is performed to select the highest and the
2nd highest clusters
The sum of the transverse energy of the candidates is
calculated
INFN Sezione di Bologna
HCAL Selection Crate
19 Clock Cycles
9
1
80 Optical Links
9
1
HSB
HSB
Master
HSB
Master
HSB
Master
7
Master
HM
HSB
Master
Master
HADRON
MASTER
1° max
2° max
1° max
2° max
HS
1430
ET
HADRON 230 LVDS
ET
SLAVE
714
16 Optical Rx
INFN Sezione di Bologna
LVDS
14 LVDS
ECAL Selection Crate
10 Cycles
The ECAL selection
2 identical cards, each
handling 14 optical and 1
LVDS inputs
1° max
30 bits
1
14 Optical Links
EM
MASTER
No cleaning of copies
No second highest then no
ghost cleaning
No SumET produced
Highest cluster from one
board goes to the 2nd for
the final selection
30 bits LVDS
1 LVDS Links
14 Optical Links
2
ES
SLAVE
1° max
ECS Control
INFN Sezione di Bologna
Hadron Master
9 cycles
6
OPTICAL
8x21
RECEIVER
222
813
SORTER
AM
max
14
ET
ECS control
8 Channels
832
OPTICAL
8x21
RECEIVER
222
813
BX-ID
8
1° max
2° max
222
22
SORTER BM
832
3
22
14
DRIVER LVDS
8 Channels
8
BX-ID
14 ET
SORTER
AM
max
14
ET
ECS control
INFN Sezione di Bologna
The AM Sorter
ECS
PAD
FPGA
XCV1000
PAD
1° max
2° max
6
8
REG
ECS
M UX
REG
REG
6
XY
Adder
E
14
INFN Sezione di Bologna
Adder
E
14
PAD
Masking
6
5
LUT
8
E-Comp
813
13
MaskCh
+Red
813
PAD
8 ch
2
LUT Add
1
Clock cycles @ 40MHz
4
3
ET
14
Sorter Logic
Auxiliary
VME Interface
Processor Logic
Electronics
ECS
Interface
Optical Interface
INFN Sezione di Bologna
FPGA
LVDS
Parallel
Sorter Logic. Tests
Pattern Generator
821-bits
Input Channels
Tektronix
TLA720
--------------To the Logic Analyzer
1st max
2nd max
sumET
INFN Sezione di Bologna
SORTEST
The Selection Board Functional Blocks
READY
Functional Blocks to be
tested
To be built in 2003
Sorter
Optical Input Interface
ECS Interface and Timing
LVDS Output Interface
ECS
TTCRx
80m
Tx
Optical Cables
Tx
Tx
8
Optical
Tx
Tx
Single Channel
Tx
Interface
Tx
Optical Tx
Tx
To be built in 2002
INFN Sezione di Bologna