Transcript TOF Electronics Overview

MTD Readout Electronics
J. Schambach
University of Texas
Hefei, March 2011
1
TOF Electronics Overview
2
The same as TOF, mostly…
• THUB, TCPU, TDIG are identical
– Each TCPU reads out 3 or 5 TDIG (1 backleg)
• MINO is a 4-NINO version of TINO
– Each MTD tray gets 1 MINO & 1 TDIG
• MTRG – this is a new card; it combines the NINO trigger
outputs logically and sends a signal to trigger: the
earliest east-end and west-end signal for each backleg
• MFTB – a new un-powered board that “closes” the gas
box (tray) and passes the MRPC signals to MINO
• There are 2 THUB, 28 TCPU, 118 TDIG, 118 MINO, and
28 MTRG boards in the MTD electronics
3
MTD Electronics Overview
4
Feed-through board “MFTB”
5
Front-End Electronics “TINO”
6
TDIG Interface
MRPC 4
(6 ch)
MRPC Interface
TINO
6
8
NINO C
6
4
8
TDIG Interface
MRPC 3
(6 ch)
MRPC Interface
2
NINO B
MRPC 2
(6 ch)
6
MRPC Interface
4
Multiplicity to TDIG PLD
(1 bit LVDS)
2
6
MRPC Interface
TDIG Interface
MRPC 1
(6 ch)
NINO A
(8 ch Amp / Disc)
Hits to HPDTC
(8 LVDS)
6
Threshold
(All Common from TDIG)
6
MINO (“MTD TINO”)
7
CERN/LAA NINO Chip
developed for ALICE
Parameter
Value
Peaking time
1ns
Signal Range
100fC – 2pC
Noise (with detector)
< 5000 e- rms
Front edge time jitter
<25ps rms
Power consumption
30 mW/ch
Discriminator threshold
Differential Input impedance
Output interface
10fC to 100fC
40Ω< Zin < 75Ω
LVDS
8
MINO
9
Digitizer Board “TDIG”
10
TDIG
11
HPTDC: Data driven TDC
•
•
•
•
•
•
•
•
Only stores data when hit detected
Variable latency over full (1/4) dynamic range
Compromise between hit rate and latency
Triggered / non triggered mode
Multiple overlapping triggers
Channel merging possible via derandomizers
Limits hit rates
Good double pulse resolution
But complicated dead time analysis
Buffer occupancies must be seriously analyzed
Buffer overflows must be handled carefully
– Hit may be lost if marked
– Complete events must never be lost
•
•
Wide latency buffer (covers full dynamic range)
More complicated architecture/implementation
Previous data driven TDC worked well in different
applications
– Logic complication handled by logic synthesis
– Extended verifications at behavioral/register/gate
level
•
Large dynamic
range
Hit
FIFO or
Dual port RAM
Trigger
time tag
Trigger
Latency
Compare time
Output
FIFO
Derandomizer FIFO’s
High flexibility
Common FIFO
12
HPTDC Time Measurement
HPTDC is fed by a 40 MHz clock giving
us a basic 25 ns period (coarse count).
A PLL (Phase Locked Loop)
device inside the chip does clock
multiplication by a factor 8 (3 bits) to
320 MHz (3.125 ns period) .
A DLL (Delay Locked Loop)
done by 32 cells fed by the PLL clock
acts as a 5 bit hit register for each PLL
clock (98 ps width LSB = 3.125 ns/32).
4 R-C delay lines
divide each DLL bin in 4 parts (R-C
interpolation)
LSB
MSB
Coarse time
(bin width 25 ns, 11 bits)
PLL bits
(bin width 3.125 ns)
DLL bits
R-C bits
(bin width 98 ps) (bin width 24.4 ps)
13
HPTDC Buffering & Readout
8 channel @ 25ps
or
32 channels @ 100ps
Level-0
Trigger
Bunch
Crossing
Hit Buffer
Level-0
Buffering
14
Tray Controller “TCPU”
15
TCPU
16
MTRG
17
DAQ/Trigger Interface THUB
National’s SerDes Chip
18
ALICE DDL Link
Front-end electronics
DDL SIU
Source
Interface
Unit
Optical Fibre
~200 meters
Destination
Interface
Unit
Read
Out
Receiver
Card
Detector
Data
Link
DDL DIU
RORC
PCI
PC
Data
Acquisition PC
J. Schambach
19
THUB
DOE Review Aug 10/11
2009
J. Schambach
20
Electronics Monitoring & Configuration Tool
J. Schambach
21
Global System Clock Distribution
22
HPTDC Readout Paths
23