CS 230: Computer Organization and Assembly Language

1 Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB 4/30/2020

Announcements

• Important announcements will be made at the beginning of the lecture • Blackboard is setup – If you cannot access, let me know immediately – Make it an interactive forum • Lectures – Will be fast paced, so read before and after the class – Stop me as soon as you have a question, or you do not understand.

• Realize that it is your last chance • Learning is your prerogative – I will skip some things that are in the textbook, and will teach somethings that are not in the textbook • Now you are in college 2 4/30/2020

More Announcements

• Green card in front of the book – Take out half an hour to browse through it • MARS – MIPS Simulator – Write programs in MIPS assembly language – Is needed for projects 1 and 2 – Start playing with MARS 3 • Quiz will be 45 mins – open book and notes – One question will be difficult • Quiz 1 – Thursday Sept 10, 2009.

– Arithmetic, Load/Store and Branch Instructions 4/30/2020

The Instruction Set Architecture (ISA)

software instruction set architecture hardware

4 ISA - The interface description separating the software and hardware .

4/30/2020

Below the Program

5

High-level language program (in C) swap (int v[], int k) . . .

Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

4/30/2020 C - Compiler Assembler

6

Higher-Level Languages

• Higher-level languages – Allow the programmer to think in a more natural language • Customized for their intended use, e.g., – Fortran for scientific computation – Cobol for business programming – Lisp for symbol manipulation – Improve programmer productivity and maintainability • more understandable code that is easier to debug and validate – Independent of • Computer on which it applications are developed • Computer on which it applications will execute • Enabler – Optimizing Compiler Technology • Very little programming at the assembler level 4/30/2020

MIPS R3000 Instruction Set Architecture

7 • Instruction Categories – Arithmetic – Load/Store – Jump and Branch – Floating Point •coprocessor – Memory Management – Special

3 Instruction Formats: all 32 bits wide OP rs rt rd OP

4/30/2020

OP rs rt Registers R0 - R31 sa PC HI LO immediate jump target funct

RISC Vs. CISC

• MIPS ISA is a RISC ISA • RISC – Reduced Instruction Set Computer • CISC – Complex Instruction Set Computer • Many differences – Will learn over the lectures • One main difference – In MIPS (a RISC architecture), all instructions are 32-bits – In IA32 (a CISC architecture), instructions can be of variable widths 8 4/30/2020

MIPS ISA: Arithmetic Instructions

• MIPS assembly language arithmetic statement

add $t0, $s1, $s2 sub $t0, $s1, $s2

• Each arithmetic instruction performs only operation • Each arithmetic instruction specifies exactly operands

destination



source1 op source2

one three 9 • All operands are contained in the – Register File

$t0, $s1,$s2 are in Register File

• Operand order is fixed 4/30/2020

Compiling More Complex Statements

10 • What is the assembler equivalent of

h = (b - c) + d

• Assume – Variable b is stored in register $s1 – Variable c is stored in $s2 – Variable d is stored in – Result is to be left in $s3 $s0

sub $t0, $s1, $s2 ## $t0 = b - c add $s0, $t0, $s3 ## $s0 = $t0 + d

4/30/2020

MIPS Register File

11 • All source operands of arithmetic instructions must be from the Register File • All the destination operands of arithmetic instructions must be written into the Register File

Register File

• Register File – Holds thirty-two 32-bit registers – Two read ports and – One write port src1 addr src2 addr 5 5 5 32 locations 32 src1 data dst addr write data 32 32 src2 data • Registers are – Faster than main memory • Register addresses are indicated by using $ 32 bits – Easier for a compiler to use • e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack – Can hold variables so that • code density improves (since register are named with fewer bits than a memory location) 4/30/2020

Register Naming Convention

0 1 2 3 4 5 6 7 $zero constant 0 (Hardware) $at reserved for assembler $v0 expression evaluation & $v1 function results $a0 arguments $a1 $a2 $a3 8 . . .

$t0 temporary: caller saves (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 25 $t8 $t9 temporary (cont’d) 26 27 28 $k0 reserved for OS kernel $k1 $gp pointer to global area 29 30 31 $sp stack pointer $fp frame pointer $ra return address (Hardware)

12 4/30/2020

MIPS ALU

32-bit • 32-bit ALU – 2 32-bit sources – 1 32-bit result 32-bit

ALU

32-bit 13 • Operations – Arithmetic •ADD, SUB, ...

– Logical •AND, OR, NOR, XOR, … 4/30/2020

How does it work?

sub $t0, $s1, $s2

src1 reg no 17 src2 reg no 18 dst addr 8 write data 15

Register File R0 R1 R8 15 R17 R18 25 10 R31

$t0  R8 $s1  R17 $s2  R18 14 • Arithmetic instructions can only change the contents of the Register File – In CISC processors, arithmetic instructions are much more powerful – they can read and change the contents of the memory 4/30/2020 25 15 10 src1 data 25 src2 data 10

MIPS R3000 Instruction Set Architecture

15 • Instruction Categories – Arithmetic – Load/Store – Jump and Branch – Floating Point • coprocessor – Memory Management – Special

Registers R0 - R31 PC HI LO



3 Instruction Formats: all 32 bits wide OP rs rt rd

4/30/2020

OP OP rs rt sa immediate jump target funct

Memory

• Arithmetic instructions operands must be registers – How do we get data into and out of memory?

• Remember, program and data reside in memory (Not in registers) – What about programs with a lot of variables?

Processor Control Datapath Memory Devices Input Output

16 4/30/2020

Accessing Memory

17 • MIPS has two basic data transfer instructions for accessing memory

lw

28

$t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory

32 (assume $s3 holds 24 10 ) • The data transfer instruction must specify – Memory address • where in memory to read from (load) or write to (store) – Register destination (source) • where in the register file to write to (load) or read from (store) • The memory address is formed by – summing the constant portion of the instruction and the contents of the second register 4/30/2020

19

Memory Organization

• How wide is the memory • What is each unit • Each unit is a bit – 0, 1 • 8-bits = 1 byte – In MIPS addressable memory – 2 32 locations of 1 byte is byte • Software likes to operate on “words” – 1 word = 4 bytes = 32 bits – 2 30 locations of 1 word

Memory

8-bit Memory 2 32 Locations 2 30 Locations 32-bit 4/30/2020

MIPS Memory Addressing

20 • The memory address is formed by summing the constant

portion of the instruction and the contents of the second (base) register

lw $t0, 4($s3)

. . . 0001

#what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where?

$s3 holds 8

. . . 0001 Memory . . . 0 1 1 0 . . . 0 1 0 1 . . . 0 0 0 1 . . . 0 0 1 0 . . . 1 0 0 0 . . . 0 1 0 0 Data in location 16 24 20 16 12 8 4 0 Word Address 4/30/2020

21

Compiling with Loads and Stores

• Assume – Variable b is stored in $s2 – Base address of array A is in $s3 • What is the MIPS assembly code for

A[8] = A[2] - b

. . .

A[3] A[2] A[1] A[0] . . .

$s3 +12 $s3 +8 $s3 +4 $s3

lw sub sw $t0, 8($s3) $t0, $t0, $s2 $t0, 32($s3)

4/30/2020

Compiling with a Variable Array Index

• Assume – A is an array of 50 elements – Base of A is in register $s4 – Variables b, c, and i are in $s1 , $s2 , and $s3 • What is the MIPS assembly code for

c = A[i] - b

22

add add add lw sub

4/30/2020

$t1, $s3, $s3 $t1, $t1, $t1 $t1, $t1, $s4 $t0, 0($t1) $s2, $t0, $s1 #array index i is in $s3 #temp reg $t1 holds 4*i #addr of A[i]

Assembly Generation: Arithmetic Instructions

• Instructions, like registers and words of data, are also 32 bits long – Example:

add $t0, $s1, $s2

– registers have numbers

$t0=$8, $s1=$17, $s2=$18

• Instruction Format: op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 23 4/30/2020

What do the field names stand for?

MIPS Instruction Fields

op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R Format

= 32 bits 24 • op opcode indicating operation to be performed • rs address of the first register source operand address of the second register source operand • rt the register destination address • rd • shamt shift amount (for shift instructions) • funct function code that selects the specific variant of the operation specified in the opcode field 4/30/2020

Assembly Generation: Load Instruction

• Consider the load-word and store-word instructions, – What would the regularity principle have us do?

– New principle: Good design demands a compromise • Introduce a new type of instruction format – I-type for data transfer instructions – previous format was R-type for register • Example:

lw $t0, 24($s2)

25 op rs rt 16 bit number 35 18 8 24 100011 10010 01000 0000000000011000 4/30/2020

I Format

Assembly Generation: Store Instruction

sw $t0, 24($s2)

op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000 26 • A 16-bit address means access is limited to memory locations within a region of  2 13 or 8,192 words (  2 15 the address in the base register $s2 or 32,768 bytes) of 4/30/2020

Assembling Code

27 • Example:

A[8] = A[2] – b lw sub sw $t0, 8($s3) #load A[2] into $t0 $t0, $t0, $s2 #subtract b from A[2] $t0, 32($s3) #store result in A[8]

• Assemble the MIPS code for these three instructions

lw sub sw

35 0 43 19 8 19 8 18 8 8 8 0 32 34 4/30/2020

28

MIPS Data Types

Bit:

0, 1

Bit String:

sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word

Character:

ASCII 7 bit code

Integers:

Unsigned Integers Signed Integers - 2's complement

Floating Point

4/30/2020

Decimal, Hexadecimal, and Binary

29 1010 1100 0011 (binary) = 0xAC3 10111 (binary) = 0001 0111 (binary) = 0x17 0x3F9 = 11 1111 1001 (binary) 4/30/2020

MEMORIZE!

00 0 0000 01 1 0001 02 2 0010 03 3 0011 04 4 0100 05 5 0101 06 6 0110 07 7 0111 08 8 1000 09 9 1001 10 A 1010 11 B 1011 12 C 1100 13 D 1101 14 E 1110 15 F 1111

Unsigned Binary Representation

30 Hex

0x00000000 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 0x00000008 0x00000009 0xFFFFFFFC 0xFFFFFFFD 0xFFFFFFFE 0xFFFFFFFF

4/30/2020 Binary

0…0000 0…0001 0…0010 0…0011 0…0100 0…0101 0…0110 0…0111 0…1000 0…1001 … 1…1100 1…1101 1…1110 1…1111

Decimal

0 1 2 3 4 5 6 7 8 9 2 32 -4 2 32 -3 2 32 -2 2 32 -1 CML

Signed Binary Representation :

31 1011 and add a 1 1010 complement all the bits -(2 3 -2 3 = - 1) = 2 3 - 1 =

2’s C binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111

4/30/2020

decimal -5 -4 -3 -8 -7 -6 5 6 7 2 3 4 -2 -1 0 1 CML

Memory Address Location

Memory

lw $t0, 24($s2) 24 10 + $s2 = . . . 1001 0100 + . . . 0001 1000 . . . 1010 1100 = 0x120040ac 0xf f f f f f f f

$s2

0x00000002 0x12004094 32 Note that the offset can be positive or negative 4/30/2020 data 0x0000000c 0x00000008 0x00000004 0x00000000 word address (hex)

MIPS Instructions, so far

Category Arithmetic (R format) Data transfer (I format) add Instr subtract load word store word Op Code 0 and 32 Example add $s1, $s2, $s3 0 and 34 35 43 sub $s1, $s2, $s3 lw $s1, 100($s2) sw $s1, 100($s2) Meaning $s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = Memory($s2+100) Memory($s2+100) = $s1

33 4/30/2020

CML

Review: MIPS R3000 ISA

Registers

34 • Instruction Categories – Arithmetic – Load/Store – Jump and Branch – Floating Point • coprocessor – Memory Management – Special • 3 Instruction Formats: all 32 bits wide

R0 - R31 PC HI LO

6 bits

OP

6 bits

OP

5 bits

rs

5 bits

rs

5 bits

rt

5 bits

rt

5 bits 5 bits

rd

5 bits

sa

5 bits

immediate

6 bits

funct

6 bits

R Format I Format OP jump target

4/30/2020

Review: MIPS Organization so far

35 • Arithmetic instructions – to/from the register file • Load/store instructions - to/from memory

Memory Processor

1…1100 Register File src1 addr 5 src2 addr 5 dst addr 5 write data 32

32 registers ($zero - $ra)

32 bits 32 src1 data 32 src2 data 32 ALU 32 32 read/write addr 32 2 30 words read data 32 write data 32 4 0 byte address (big Endian) 5 1 6 2 32 bits 7 3 0…1100 0…1000 0…0100 0…0000 word address (binary) 4/30/2020

Review: Naming Convention for Registers

0 1 2 3 4 5 6 7 $zero constant 0 (Hardware) $at reserved for assembler $v0 expression evaluation & $v1 function results $a0 arguments $a1 $a2 $a3 8 . . .

$t0 temporary: caller saves (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 25 $t8 $t9 temporary (cont’d) 26 27 28 $k0 reserved for OS kernel $k1 $gp pointer to global area 29 30 31 $sp stack pointer $fp frame pointer $ra return address (Hardware)

36 4/30/2020

37

MIPS Data Types

Bit:

0, 1

Bit String:

sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word

Character:

ASCII 7 bit code

Integers:

Unsigned Integers Signed Integers - 2's complement

Floating Point

4/30/2020

Yoda says…

38 • Named must your fear be before banish it you can 4/30/2020