FPGA Routing

 Pathfinder

[Ebeling, et al., 1995]

   Introduced negotiated congestion During each routing iteration, route nets using shortest path  Allows overuse resources (congestion) of routing If congestion exists (illegal routing)   Update cost of congested resources based on the amount of overuse Rip-up all routes and reroute all nets 1 1 1 1 1 1 1 1 congestion 1

FPGA Routing

 VPR – Versatile Place and Route

[Betz, et al., 1997]

  Uses modified Pathfinder algorithm Increase performance over original Pathfinder algorithm   Routability-driven routing  Goal: Use fewest tracks possible Timing-driven routing  Goal: Optimize circuit speed Route Rip-up yes Done!

no Routing Resource Graph Graph 2

JIT FPGA Routing

 Riverside On-Chip Router (ROCR)    Represent routing nets between CLBs as routing between SMs Resource Graph   Nodes correspond to SMs Edges correspond to channels between SMs  Capacity of edge equal to the number of wires within the channel Requires much less memory than VPR as resource graph is much smaller 0/4 0/4 SM 0/4 0/4 0/4 SM 0/4 0/4 0/4 0/4 SM 0/4 SM 0/4 0/4 SM 0/4 SM 0/4 0/4 0/4 SM 0/4 SM 0/4 SM 3