Transcript Šiuolaikinių kompiuterių architektūra

COMPUTER
ARCHITECTURE
(P175B125)
Assoc.Prof. Stasys Maciulevičius
Computer Dept.
[email protected]
Data transfers

Multiplexed read :
Address

Access
time
Data
Multiplexed write :
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Address
Data
(1st cycle)
(2nd cycle)
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Data transfers

Nonmultiplexed read:
Address
Data

Address and data
are transferred
through separate
buses
Nonmultiplexed write :
Address
Data
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Data transfers

Read-modification-write:
Address

Data read
Data written
Data block transfer:
Address
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Data0
Data1
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Data2
Data3
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Concept of a bus


A bus, in computing, is a set of physical connections
(cables, printed circuits, etc.) which can be shared by
multiple hardware components in order to communicate
with one another
The purpose of buses is to reduce the number of
"pathways" needed for communication between the
components, by carrying out all communications over a
single data channel
Point-to-point
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Bus
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Ports



If only two hardware components communicate
over the line, it is called a hardware port (such
as a serial port or parallel port)
Typically, a personal computer is provided with
one or more serial ports and usually one
parallel port
The serial port supports sequential, one bit-at-atime transmission to peripheral devices such as
scanners and the parallel port supports
multiple-bit-at-a-time transmission to devices
such as printers
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Buses within a computer

There are generally two buses within a
computer:

the internal bus (sometimes called the frontside bus, or FSB). The internal bus allows the
processor to communicate with the main
memory (the RAM).
 the expansion bus (sometimes called the
input/output bus) allows various motherboard
components (USB, serial, and parallel ports,
cards inserted in PCI connectors, hard drives,
CD-ROM and CD-RW drives, etc.) to
communicate with one another
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Front Side Bus
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Bus subassembly

In reality, each bus is generally constituted of 50
to 100 distinct physical lines, divided into three
subassemblies:



The address bus transports memory addresses
which the processor wants to access in order to read
or write data
The data bus transfers instructions coming from or
going to the processor. It is a bidirectional bus.
The control bus transports orders and synchonisation
signals coming from the control unit and travelling to all
other hardware components. It is a bidirectional bus,
as it also transmits response signals from the hardware
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System with Pentium 4
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Old buses - ISA
ISA (Industry Standard Architecture)
 8 data lines (8088, 4.77 MHz)
 In 1984 extended - 16 lines (for 80286,
8 MHz)
 Slow, but have a lot of peripheral
devices
 8-bit boards (cards) use part of lines
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Old buses - EISA
EISA (Extended Industry Standard
Architecture)




bus standard for IBM compatible
computers
EISA extends the AT bus to 32 bits and
allows more than one CPU to share the
bus
effective bus arbitration
automatic configuration of adapter cards
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PCI bus
PCI (Peripheral Component Interconnect)


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


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

developed by Intel in 1992
computer bus for attaching hardware devices in
a computer
32 data lines (PCI 2.1 – 64 data lines)
33 MHz (PCI 2.1 – 66 MHz)
fastest among general I/O buses
supports burst mode
effective bus arbitration
systems have 3-4 PCI connectors
transfer speed – from 133 MB/s to 532 MB/s
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AGP bus
The AGP bus (short for Accelerated
Graphics Port)




was released in 1997
AGP bus is directly linked to the processor's FSB and
uses the same frequency, for increased bandwidth
was developed specifically to connect with the video
card
cards which employ this graphics bus theoretically
require less on-board memory; because they can
directly access graphical data (such as textures) stored
in central memory
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AGP bus

AGP is based on the 66 MHz PCI bus
specifications but is further enhanced by:

allowing deeply pipelined memory read and
write operations, thus masking memory
access latencies
 demultiplexing (separating) address and data
on the bus, thus allowing the bus to be more
efficiently utilized
 allowing data transfers on both rising and
falling edges of the signal, thus doubling the
throughput of the bus (AGP2x)
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AGP bus
PCI sends address and waits on data; then new
access starts
AGP can send package of addresses, after some
time it appears the data package. According to
AGP specification package can be up to 256
requests
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AGP bus



Version 1.0 of the AGP bus had a 1x
mode that could send 8 bytes every two
cycles, and a 2x mode for transferring 8
bytes per cycle
In 1998 was added AGP 4x, which could
send 16 bytes per cycle
AGP in 2002 doubled the speed with a
new AGP 8x mode
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AGP bus

The transfer speeds for the various AGP
standards are:





AGP 1x: 66.66 MHz x 1 x 32 bits /8 = 266.67 MB/s
AGP 2x: 66.66 MHz x 2 x 32 bits /8 = 533.33 MB/s
AGP 4x: 66.66 MHz x 4 x 32 bits /8 = 1.06 GB/s
AGP 8x: 66.66 MHz x 8 x 32 bits /8 = 2.11 GB/s
Now these speeds seems to be
insufficient, thus PCI Express repaces
AGP in our PCs
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AGP bus vs PCI
AGP
PCI
Pipelined Requests
Address/Data de-multiplexed
Peak at 533 MB/s in32 bits
Single target, single master
Memory read/write only.
5 No other input/output
operations
6 High/low priority queues
1
2
3
4
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Non-pipelined
Address/Data multiplexed
Peak at 133 MB/s in 32 bits
Multi target, multi master
Link to entire system
No priority queues
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PCI Express bus
PCI Express bus (written PCI-E or 3GIO for "Third
Generation I/O"), is an interconnect bus that
allows to add expansion boards to a computer

developed in 2002

runs in serial interface

comes in several versions (1x, 2x, 4x, 8x, 12x,
16x and 32x), which provide

throughputs of between 250 MB/s and 8 GB/s
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PCI Express


PCI Express uses bidirectional serial link "pointto-point”, which is called the
lane
PCI Express connects two
devices with channel,
consisting of one line
(marked 1x) or several lines
(2x, 4x, 8x, 12x, 16x and
32x)
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PCI Express vs PCI
PCI Express
Graphics
PCI
Memory
bridge
Graphics
Memory
bridge
I/O bridge
I/O bridge
Switch
Device
Device
Device
Device
Switch
Device
Device
Device
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Device
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PCI Express

It differs from the PCI greater information
transfer rate (up to 8 GB / sec.), lower supply
voltage (0.8 V) and the fact that there is a serial,
bi-directional (1x), capable to transmit data with
speed 250 megabits per second
PCI Express mode
1x
Bandwidth in one
direction, GB/s
0, 25 0,5
Bandwidth in both
directions, GB/s
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0,5
2x
1
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4x
8x
12x
16x
32x
1
2
4
6
8
2
4
6
8
16
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Characteristics of a bus

A bus is characterised by the amount of information that
can be transmitted at once. This amount, expressed in
bits, corresponds to the number of physical lines over
which data is sent simultaneously. A 32-wire ribbon
cable can transmit 32 bits in parallel. The term "width" is
used to refer to the number of bits that a bus can
transmit at once

Additionally, the bus speed is also defined by its
frequency (expressed in Hertz), the number of data
packets sent or received per second. Each time that data
is sent or received is called a cycle
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Characteristics of a bus

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This way, it is possible to find the maximum
transfer speed of the bus, the amount of data
which it can transport per unit of time, by
multiplying its width by its frequency
A bus with a width of 16 bits and a frequency of
200 MHz, therefore, has a transfer speed equal to:




16 * 200.106 = 3200*106 bit/s, or
3200*106/8 = 400*106 bytes/s or
400*106 /1024 = 322,6*103 KB/s or
322,6*103 /1024 = 315 MB/s
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Characteristics of a buses
Bus
Data lines
Frequency
(MHz)
Transfer speed
(MB/s)
8-bit ISA
8
8.33
4.2
16-bit ISA
16
8.33
8.4
EISA
32
8.33
33
VLB
32
33
133
PCI
32
33
133
64-bit PCI
64
66
533
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Characteristics of a buses
Bus
Data
lines
Frequency
(MHz)
Transfer speed
(MB/s)
64-bit PCI
AGP
64
32
66
66
533
266
AGP (2 mode)
AGP (4 mode)
AGP (8 mode)
PCI Express 1.
32
32
32
16
66  2
66  4
66  8
1,25 GHz
533
1066
2130
8 GB/s
PCI Express 2.0
PCI Express 3.0
16
16
2,5 GHz
5 GHz
16 GB/s
32 GB/s
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HyperTransport technology
HyperTransport Technology is a high-speed, low
latency, point-to-point link designed to increase the
communication speed between integrated circuits
in computers, servers, embedded systems
HyperTransport Technology is designed to:




Provide significantly more bandwidth than current
technologies
Use low-latency responses and low pin counts
Maintain compatibility with legacy PC buses
Appear transparent to operating systems and offer little
impact on peripheral drivers
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Features of HT
Feature/ function
Description
Bus type
Dual, uniditectional, “point-to-point”
Bus width
2, 4, 8, 16 or 32 bits
Protocol
Packet, packet size – nx4 bytes
Bandwidth (at 200
MHz)
From 100 to 6500 MB/s in each
direction
Frequency can be higher – up to 800 MHz
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HyperTransport 3.0
HyperTransport 3.0 adds the following new
clock rates, keeping compatibility with HT1
and HT2 rates (transfer rates assuming 16bit links, which is the configuration used by
AMD processors):

1,800 MHz = 3,600 MT/s = 7,200 MB/s
 2,000 MHz = 4,000 MT/s = 8,000 MB/s
 2,400 MHz = 4,800 MT/s = 9,600 MB/s
 2,600 MHz = 5,200 MT/s = 10,400 MB/s
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Features of HT versions
HT
Version
Year
Max. HT Max. Bandw. Max. Bandw. Max. Bandw.
Frequency
(bi-dir.)
at
at
16-bit unidir. 32-bit unidir.
1.0
2001 800 MHz 12.8 GB/s 3.2 GB/s
6.4 GB/s
2.0
2004 1.4 GHz
22.4 GB/s 5.6 GB/s 11.2 GB/s
3.0
2006 2.6 GHz
41.6 GB/s 10.4 GB/s 20.8 GB/s
3.1
2008 3.2 GHz
51.2 GB/s 12.8 GB/s 25.6 GB/s
Maximal link width – 32-bit
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HyperTransport links
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Using HyperTransport
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HyperTransport 3.1


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HyperTransport 3.1 specification extends the 2.6 GHz
maximum clock speed of HyperTransport 3.0 to 3.2
GHz
This increase together with HyperTransport’s double
data rate (DDR) capability delivers up to 6.4
GigaTransfers/second (GT/s) per bit and yields
aggregate performance of 51.6 gigabytes per second
(GB/s)
The HyperTransport 3.1 specification defines three
new clock rate steps of 2.8 GHz, 3.0 GHz and 3.2 GHz.
This increase in clock speed delivers a 23 percent
increase in aggregate bandwidth
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QuickPath Interconnect (QPI)


Since the beginning of times Intel CPUs use an
external bus called Front Side Bus or simply FSB
that is shared between memory and I/O requests
The next generation of Intel CPUs will have an
embedded memory controller and thus will provide
two external busses:
a
memory bus for connecting the CPU to the memory
and
 an I/O bus to connect the CPU to the external world. This
bus is a new bus called QuickPath Interconnect (QPI)
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QuickPath Interconnect
Intel introduced QuickPath Interconnect in
Nehalem microarcitecture (instead of the
previously used FSB)
 Intel has done 5 years later than AMD
entered the HyperTransport
 For the first time this type of bus appeared
even earlier, when the DEC engineers, the
created the Alpha 21364

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QuickPath Interconnect


The first version of the QPIwill work with a clock
rate of 3.2 GHz transferring two data per clock
cycle (a technique called DDR, Double Data Rate),
making the bus to work as if it was using a 6.4 GHz
clock rate (Intel uses the GT/s unit – which means
giga transfers per second – to represent this).
Since 16 bits are transmitted per time, we have a
maximum theoretical transfer rate of 12.8 GB/s on
each lane (6.4 GHz x 16 bits / 8).
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USB – Universal Serial Bus
The USB – Universal Serial Bus implements
communication between a computer and
peripheral devices

It gives a single, standardized, easy-to-use way to
connect up to 127 devices (keyboard, printers,
scanners, sound systems, ...) to a computer

USB is intended to replace many varieties of
serial and parallel ports
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USB
There are three physical parts to the USB system.
These include:

the host (computer),

hubs, and

devices.
All connectors are one-size-fits-all, so a device can be
plugged directly into the host, or into a hub, which
in turn is plugged into the host
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USB features

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The computer acts as the host
Up to 127 devices can connect to the host, either
directly or by way of USB hubs
Individual USB cables can run as long as 5 meter
A USB cable has two wires for power (+5 volts and
ground) and a twisted pair of wires to carry the data
On the power wires, the computer can supply up to
500 milliamps of power at 5 volts
Low-power devices (such as mice) can draw their
power directly from the bus. High-power devices (such
as printers) have their own power supplies and draw
minimal power from the bus
USB devices are hot-swappable, meaning you can
plug them into the bus and unplug them any time
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USB specifications



The original USB 1.0 specification was
introduced in 1996. It had a data transfer
rate of 12 Mbit/s
The USB 2.0 specification was released in
April 2000. Data transfer rate was increased
to 480 Mbit/s
The USB 3.0 (SuperSpeed USB)
specification was released in 2008. Its
maximum transfer rate is up to 10 times
faster than the USB 2.0 release
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USB specifications

Compare the USB speed:
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Processor and chipset
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Chipsets - MCH

The central hub
for the data traffic
in an Intel
architecture
system is the
Memory
Controller Hub
(MCH)
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Chipsets - ICH


The Direct Media Interface (DMI) in the MCH is a
dedicated serial link to the I/O Controller Hub
(ICH). The DMI link is actually four serial links, with
dedicated transmit and receive pins
The iGFX is a dedicated link to the graphic device
(interface for Intel graphics cards)
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Chipsets - ICH

The second
part of
chipset
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Chipsets - ICH


The I/O Controller Hub (ICH) provides extensive
I/O support, support for legacy peripherals dating
back to the 1980s, and integrates support for key
platform management functions such as power
sequencing and ACPI power management, fan
speed control, and reset timing
The ICH acts a bridge or controller for a variety of
industry standard interfaces allowing the system
designer to choose from a wide range of
peripherals
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Chipsets - ICH
PCI interface operates at 33MHz and
allowing for a number of external bus
masters. The ICH acts as the central arbiter
and root of the PCI bus.
 PCI Express* root port controllers. The
number of ports varies with the product but is
generally in the range of 1 to 4. Link widths of
x1 x4 are support at speeds of 2.5GB/s.

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Chipsets - ICH


Serial ATA (SATA) controllers supporting both
legacy operation using I/O space and the
Advanced Host Controller Interface (AHCI) using
memory mapped I/O as well as allowing advanced
features such has hot-plug and native command
queuing. SATA II supports data rates of 1.5 Gb/s
and 3 Gb/s
Universal Serial Bus (USB) supporting High
Speed USB 2.0 (480 Mb/s) operation as well as
full-speed (12 Mb/s) and low-speed signaling
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Chipsets - ICH


Integrated Drive Electronics (IDE) controllers are
also used to control hard disc drives, and CD/DVD
drives. They have been replaced in some
platforms by the newer SATA interface since it
offers better performance over a smaller interface
General Purpose I/O (GPIO) pins for system
customization. Many pins can also be configured
to cause interrupts or wake events
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Chipsets - ICH


System Management Bus (SMBus 2.0) The
SMBus Host interface allows the processor to
communicate with SMBus slaves. This interface is
also compatible with most I2C devices. Hence, the
host controller supports eight command protocols of
the SMBus interface
Serial Peripheral Interface (SPI) is used to
interface to BIOS flash devices which contain the
boot firmware and initialization code. Up to 2 SPI
flash devices operating at 33 MHz can be
connected
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Chipsets - ICH


Low Pin Count Interface (LPC) This interface
replaces the ISA bus originally developed by IBM
in the early 1980s, but uses only 7 signals plus a
clock. It can be used to connect to a variety low
speed devices that don’t require the bandwidth of
PCI or PCI Express* (floppy driver controller, PS2
keyboard/mouse controls and serial ports)
JTAG Boundary Scan allows testing of PCB
board after assembly
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Intel Atom and chipset
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Bus arbitration

In a single bus architecture when more than one
device requests the bus, a device required to
decide who gets the bus
S1
S2
D
I11
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Dm
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Bus arbitration



Such a device is called bus arbiter
Bus Arbitration – the decision process and an
elaborate system for resolving bus control conflicts
and assigning priorities to the requests for control of
the bus
Bus Mastering – a method of enabling different
device controllers on the bus to ‘talk’ to one an
other, without having to go through the CPU
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Bus arbitration methods

Centralized. Centralized bus arbitration
requires hardware (arbiter) that will grant the bus
to one of the requesting devices. This hardware
can be part of the CPU or it can be a separate
device on the motherboard
 Decentralized. Decentralized arbitration there
isn't an arbiter, so the devices have to decide
who goes next. This makes the devices more
complicated, but saves the expense of having an
arbiter
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Centralized bus arbitration
Request
Bus
Grant
Controlling bus
owning
Request
Grant
Controlling bus
owning
Request
Grant
Controlling bus
owning
arbiter
3
2
1
REQUEST3
REQUEST2
REQUEST1
REQUEST0
GRANT3
GRANT2
GRANT1
GRANT0
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Decentralized bus arbitration
Request
Permission
to use bus
Grant
IN#
OUT#
Bus arbiter 0
Request
Grant
IN#
Bus arbiter 1
OUT#
BUSY#
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