Transcript Slide 1

ATE Debugging tool
효율적 테스트/디버그를 위한 디자인과 테스트 업체의 연구 방안
Korea Test Conference
Jin-Soo Ko
([email protected])
June 25, 2014
SW AND DEBUG TOOLS MAGNIFY
NEEDLE!
MARKET TRENDS DRIVING ATE SW TOOL ROADMAP
Complex Flows
Quality
<100 DPM For Mobility Devices
Increased Device
Configuration and Repair
Functional
Integration
COT Pressures
Higher Multisite,
Concurrent Test, Datalog
overhead
Large Test Lists
Collaborative
Development
Shorter Time To
Market
Less Than 15 Days Si to
Samples
3
Test Engineer
Faster Time To
Volume
>1M devices within
2 Months
IG-XL: #1 IN ATE SOFTWARE - WHY NEED GOOD SW-DEBUG TOOL?
IG-XL has been ranked #1 in ATE Software for the last four years
by VLSI Customer Satisfaction Research Survey
30% faster test program development time
Native MultiSite, Program Modularity, Templates, “Debug in
the Zone”, Complete tool set, ESA
Optimal throughput early in the product ramp resulting in
faster time to profits.
IG-XL’s Pure Parallel, Native MultiSite, Background DSP,
TrueCT, Timelines
Faster time to entitled yield
Scan fail capture throughput, APIs to design environments,
Protocol Aware
Better quality programs that result in fewer RMAs and
defect escapes
VBT, Spike-Check tool, Simulation Tools, IG-Review, IG-Diff
New users become self
sufficient faster
Easy to learn programming language, DUT Centric use
model, Template programming
DESIGN  TEST  DESIGN LOOP
Failure Analysis / Yield Enhancement
“on tester”
tools
Simulation
Design
“off tester”
tools
On-Tester Debug/
Characterization
(hours/minutes)
events
ATPG
STDF
•Timing/Levels
•Mixed Signal
•Repeatability
•Correlation
Pattern & Test
program. Gen.
transactions
EDA-based Pattern Viewer
• Simultaneous display of EDA and tester information
• Diagnose Physical Device Faults
5
HOW ARE SCAN FAILURES RESOLVED NOW?
•
Tools are not integrated
•
Information is lost or delayed between Test / Design / FA
•
Investigations can take weeks to complete
6
THE TESTER IS ONLY PART OF A BIGGER PROCESS
Advanced ATE SW tools for Time to Market
OPENEDA: CONNECTING ATE SW (IG-XL) TO THE ENTIRE DESIGN
AND TEST ENVIRONMENT
High Volume Manufacturing:
Test Floor Management
Factory Data Management
Adaptive Test
Part Average Testing
Operator Interfaces
Peripherals and Handlers
Yield Monitoring
OEE
Design and Test Development:
EDA Links
Test Program Generation
Feedback To Simulation
Test-Design Integration
Yield Learning
Data Analysis
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WHAT THE TEST
ENGINEER SEES…. POP
Since the Engineer can control all the events from
one pattern, we have Pattern Oriented
Programming (POP)
Program Instruments
with Psets (All
instruments in parallel)
Select Source Signal
Trigger measurements at
precise times
Exact
Timeline
Automatic data move
and processing
Reprogram Instruments
with PSets
Select different Source
Signal
Trigger measurements at
precise times
Automatic data move
and processing
…and so on…
9
-3dB
CONCURRENT TEST TOOL
Timeline viewer
Concurrent Test Flow
Serial Test Flow
Initial
Initial
Tests
Block A
Tests
Block B
Test
Time
Tests
Block C
Tests
Block D
Tests
Block E
Tests
Block F
Full Functional
Test
10
Tests
Block A
Test
Time
Tests
Block C
Tests
Block B
Tests
Block E
Tests
Block D
Tests
Block F
Full Functional
Test
Development Challenges
• Common bus/pins
• Shared test resources
• Flow manipulation
• Multi-site implementation
• Adaptive test & Retest
• Debug tools
MULTI-SHEET USE MODEL
= no more manual merging of sub programs
• Separate test code & data for each sub program
• Tied together at the Job List Sheet
• IG-XL 8.10.11 completes the Multi-Sheet Model
Sub-Program A
•Enabler for independent development
•Reduces time to integrate
Sub-Program B
RF TOOLS- LTE-A TX SIGNAL DEBUG TOOL AND RESULT
IG-XL 7.30
IG-XL 7.40
• ESA 2.0
• ESA 2.5
3GPP LTE
3GPP LTE Update
TD-SCDMA
Bluetooth 3.0
802.11n 4x4 MIMO
VSA 11
VSA 10.01
• 1 port vector
• Power de-embedding
• Signal sheet support
• Smith charting
IG-XL 8.00.01
IG-XL 8.10
IG-XL 8.20
• ESA 3.0
LTE 8.9
VSA12
• ESA 3.5
LTE-A (R10)
802.11ac
VSA 14
• ESA 4.0
LTE-A (100MHz)
802.11ac (160MHz)
802.11ac (80+80)
BT 4.0 (LE)
VSA 16
• 90% reduction in VSA
instance creation times
PROTOCOL AWARE
“Stored Response” ATE
Complex Device Architecture
Tries to
Test
USB
I/F
Power Mgmt
Functions
Audio / BB
Functions
DRAM
I/F
3G RF
CPU
DSP
BB
Proc
Flash
I/F
Write.jtag ( ADDR: 04h, DATA: 55h)
Read.jtag (ADDR: 0Ah, DATA  read_var)
JTAG
I/F
WiFi
FM/TV
Integrated Mobile Device
Protocol Studio
For online debug of
protocol transactions
•Transaction results
•Debug displays
Protocol Definition Editor
For defining and modifying
protocols
GPS
•Data capture setups
•Module management
•Port Properties