Transcript No Slide Title

How to reduce the power dissipation?
Ptotal  T  Cload V
2
DD
 fCLK VDD (I short circuit  Ileakage  I static )
Voltage Scaling
Switched Capacitance
Switching Activity
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Low-Power Design Through Voltage Scaling
 Different from constant-field scaling (Full Scaling)
–
Full Scaling: power supply, as well as device dimension
and doping density are scaled by the same factor.
–
Voltage Scaling: key device parameters and the load
capacitances are constant.
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Low-Power Design Through Voltage Scaling
 Influence of Voltage Scaling on Power and Delay
– Dynamic power dissipation is reduced significantly.
Pavg  T  Cload V 2 DD  fCLK
– Propagation delay time increase if all the other
parameters are kept constant.
 PHL 
 PHL
 2VT .n

Cload
4(V  V )

 ln( DD T .n  1)
kn (VDD  VT .n ) VDD  VT .n
VDD

 2V

4(VDD  VT . p )
Cload
T.p


 ln(
 1)

VDD
k p (VDD  VT . p ) VDD  VT . p


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Low-Power Design Through Voltage Scaling
Can we compensate for the delay caused by reducing the
supply voltage?
Solution: Scale down the threshold voltage of the transistors ( VT).
Positive Influence:
– when scaled linearly, allow the circuit to produce the same
speed-performance at a lower Vdd. example
Negative Influence:
– noise margin
and subthreshold conduction.
(V V ) / nV
I leakage  I 0e
gs
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th
T
4
Low-Power Design Through Voltage Scaling
How to overcome the difficulties (leakage and high stand-by
power dissipation) associated with the low –VT circuits?
Solution:
– Variable-Threshold CMOS Technique (VTCMOS)
– Multiple-Threshold CMOS Technique (MTCMOS)
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Low-Power Design Through Voltage Scaling
 Variable-Threshold CMOS Technique (VTCMOS)
VT  VT 0    (  2 F  VSB  2 F )
– Conventional CMOS logic circuit: substrate terminals are
connected to Vdd or Vss. VT not influenced by the body effect.
– VTCMOS logic circuit : VSB are variable and generated by
a variable substrate bias control circuit.
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Low-Power Design Through Voltage Scaling
 Drawbacks of VTCMOS technique
 Requires twin-well or triple-well to apply different
substrate bias voltage to different parts of the chip.
 Separated power pins may be required if the substrate
bias voltage levels are not generated on-chip.
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Low-Power Design Through Voltage Scaling
 Multiple-Threshold CMOS Technique
Using two different types of transistors with two different
threshold voltages in the circuit.
– Low-VT transistors: design the logic gates where speed is
essential.
– Stand-by transistors (Sleep transistors) : isolate the logic
gate in stand-by mode to prevent leakage dissipation.
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Low-Power Design Through Voltage Scaling
 Drawbacks of MTCMOS circuit design technique
 Fabricate two different VT transistors on the same chip
 Sleep transistors increase the area and parasitic capacitance.
 MTCMOS is easier to implement and use compared to the
VTCMOS.
What can we do if both MTCMOS and VTCMOS are
infeasible due to the technological limitations?
Using system-level architectural methods (pipelining and
Solution: hardware replication ) to maintain the system performance
(throughout) despite the voltage scaling.
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Low-Power Design Through Voltage Scaling
 Pipelining Technique
 Single Stage Structure
Register
Register
Logic Function
F(input)
Input
Output
tCLK
tCLK
CLK
Input
Output
Input1
Input2
Input3
Input4
Input5
Input6
Input1
Input2
Input3
Input4
Input5
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Low-Power Design Through Voltage Scaling
 N-Stage Pipeline Structure
Register
Stage1 Register Stage2
Stage N
…
Input
tCLK
Output
Output
tCLK
tCLK
…
CLK
Input
Register
Input1
Input2
Input3
…
…
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InputN
Input1
InputN+1
InputN+2
Input2
Input3
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Low-Power Design Through Voltage Scaling
Theory: – Assuming all stages have approximately equal delays.
– Maintaining the same function throughput as single stage.
– Then, the logic blocks between two successive registers
can operate N-times slower.
– This means the power supply voltage can be reduced to a
value of VDD.new to effectively to slow down the circuit .
– Drawback of Pipeline Technique
–N-1 register arrays are introduced, area increase.
– Increases the latency from one to N clock cycles.
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Low-Power Design Through Voltage Scaling
 Parallel Processing Approach (Hardware Replication)
Input
Logic
Function
F(input_1)
…
CLK
CLK_1 (fCLK/N )
Input
Input
Logic
Function
F(input_2)
MUX
Input1
Input2
Output
CLK_2 (fCLK/N )
…
CLK_2
…
CLK_N
Output
InputN+1
…
…
…
Input
Logic
Function
F(input_N)
InputN
TCLK_i= N x TCLK
CLK_1
SELECT fCLK
…
x
x
…
x
Input1
CLK_N (fCLK/N )
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Low-Power Design Through Voltage Scaling
Theory: – Gated clock signals(NTCLK) are used to load each register.
– Each one of N inputs are loaded into a different register.
– Time allowed to compute the function for each input
vector is increased by a factor of N.
– This means the power supply voltage can be reduced to a
value of VDD.new to effectively slow down the circuit .
– Drawback of Hardware Replication
– input/output routing capacitance
– increased area and latency
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Estimation and Optimization of Switching Activity
 The Concept of Switching Activity
2
Pavg  T  Cload VDD  fCLK
aT (switching activity factor): effective number of powerconsuming voltage transition experienced by the output
capacitance per clock cycle. Depends on the circuit topology,
logic style, and input signal statistics.
How to investigate the output transition probabilities for
different types of logic gates?
Solution: Introduce two signal probabilities
– P0: probability of having a logic “0” at the output.
– P1:probability of having a logic “1” at the output. (P1=1-P0)
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Estimation and Optimization of Switching Activity
Power-consuming transition probability is :
P01= P0 . P1
Example:
a static CMOS NOR2
– General case of a static CMOS logic gate with n input variables
P01= P0.P1= (n0/2n).(2n-n0)/2n
n0: number of zeros in the output column of the truth table.
Example:
transition probability is a function of the number of inputs.
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Estimation and Optimization of Switching Activity
– In Multi-Level Logic Circuits
– Distribution of input signal probabilities is not uniform.
– Output transition probability becomes a function of the
input probability distributions.
– Evaluation of switching activity becomes a complicated
problem in large circuits.
– Designer rely on CAD tools for correct estimation .
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Estimation and Optimization of Switching Activity
– Transition probability in dynamic CMOS logic circuit.
– Power is consumed whenever the output value equals “0”.
– Power consumption is determined by the signal-value
probability and not by the transition probability
– Signal-value probability is always larger than transition
probability.
– power consumption of dynamic CMOS logic gates is typically
larger than static CMOS gates under the same conditions.
 Reduction of Switching Activity
– Algorithmic Optimization
Example: bubble sort Vs merge sort
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Estimation and Optimization of Switching Activity
– Architecture Optimization
An important measure is based on delay balancing and the reduction
of the glitches. (What is glitch, where does it come from?)
Example: F  A  B  C  D
Chain Structure
suffer glitching, more power
dissipation.
Tree Structure
no glitch, less power dissipation,
even smaller propagation delay.
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Estimation and Optimization of Switching Activity
– Circuit-level Optimization
An effective design technique is using gated clock signals.
Recall: Power dissipation in the clock distribution network can
be very significant.
Example: Design an N-bit number comparator circuit using gated
clock. The circuit compares the magnitudes of two
unsigned N-bit binary number (A and B) and produces an
output to indicate which one is larger.
Conventional approach: All input bits are latched into two Nbit registers, and then applied to the comparator circuit. Two
N-bit register arrays dissipate power in every clock cycle.
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Estimation and Optimization of Switching Activity
Gated clock signals approach:
How much the
overall switching
power dissipation of the
system can be reduced
if the incoming binary
numbers are randomly
distributed?
Solution:
ENGG 6090 Topic Review
50%
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Welcome Shaw back!
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Low-Power Design Through Voltage Scaling
Variation of the
normalized
propagation
delay of a CMOS
inverter, as a
function of the
power supply
voltage Vdd and
the threshold
voltage VT.
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Low-Power Design Through Voltage Scaling
VTp={
-0.2 V in active mode
VBp={
-0.6 V in stand-by mode
2 V in active mode
4 V in stand-by mode
2V
Vin
VTn={
0.2 V in active mode
0.6 V in stand-by mode
Substrate
Bias Control
Circuit
Vout
VBn={
0 V in active mode
-2 V in stand-by mode
ENGG 6090 Topic Review
– Active mode:
VBn=Vss, VBp=Vdd.
Low power
dissipation (low Vdd)
and high switching
speed (low VT).
– Stand-by mode:
lower VBn,
higher VBp.
VTn and | VTp| increase.
I leakage  I 0e
(Vg s Vth ) / nVT
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Low-Power Design Through Voltage Scaling
VDD
stand-by
high- VT prevents subthreshold
leakage in stand-by
pMOS
mode
CMOS
Logic with
low VT
stand-by
high-speed operation
with low power
consumption
high- VT prevents subthreshold
nMOS leakage in stand-by
mode
– Active mode: sleep
transistors on, low VT logic
gates operate with low
switching power dissipation
and small propagation delay.
– Stand-by mode: sleep
transistors off, conduction
paths for any subthreshold
leakage that may originate
from the internal low-VT
circuitry are cut off.
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Estimation and Optimization of Switching Activity
3/4 * 1/4 = 3/16
1/4 * 1/4 = 1/16
3/4 * 3/4 = 9/16
0
1
3/4 * 1/4 = 3/16
If the two inputs are independent and uniformly distributed, then
P0=3/4 P1=1/4
The probability that a power-consuming transition occurs at the
output node is
P01=P0.P1= 3/16
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Output Transition Probability
Estimation and Optimization of Switching Activity
0.30
NAND/NOR:
only one “0” or
“1” at truth table.
0.25
Transition probability
for XOR/XNOR gate
0.20
0.15
0.10
Transition probability
for NAND/NOR gate
XOR/XNOR:
0.05
0.00
2
3
4
5
6
Number of Inputs
7
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equal number of
“0” and “1” at
truth table.
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Glitch
– Primarily due to a mismatch or imbalance in the path lengths in
the logic network .
– Such a mismatch results in a mismatch of signal timing with
respect to the primary inputs.
– If all input signal of a gate change simultaneously, no glitch.
– When glitch happens, a node exhibit multiple transitions in a
single clock cycle before settling to the correct logic level. This
contribute to the dynamic power dissipation.
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