Transcript Lecture 14 Finite State Machine Implementation

Lecture 16
Introduction to VHDL
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
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Outline
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VHDL Language Basics
Interface
Architecture Body
Behavioral VHDL
Various Sequential Statements
Process Statements
Delay Models
READING: Dewey 11.2, 11.3, 11.4, 11.5. 11.6,
15.1, 15.2, 18.2, 18.3, 18.4, 18.5
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Modeling Digital Systems
• Digital system: Any digital circuit that processes
or stores information in digital form: gates to
functional units
• Model represents only relevant information and
abstracts away irrelevant detail
• Model needed to:
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Develop and specify requirements
Communicate understanding of a system to a user
Allow testing of design through simulation
Allow formal verification
Allow automated synthesis
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What is VHDL
• (Very High Speed Integrated Circuits) VHSIC
Hardware Description Language
• Used for two things
– (1) Used to model digital systems, designs can then be
SIMULATED
• A simulator runs a VHDL description computing the outputs of
a modeled system
– (2) Used as a language to enter designs into CAD
tools, designs can then be SYNTHESIZED
• VHDL also provides a blackboard for designing digital
systems
• An initial design is progressively expanded and refined
• Another popular hardware language is Verilog
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Relationship between VHDL and
hardware
VHDL
description
Simulator
Model
Simulated / actual
outputs
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Hardware
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Domains and Level of Modeling
Structural
Functional
Register transfer
Algorithm
Gates
Register Transfer Level
Transistor
Boolean Equation
Polygons
Standard Cells
Floorplan
Geometric
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VHDL Modeling Concepts
• VHDL Includes facilities for describing the
FUNCTION and STRUCTURE
• At Various levels from abstract to the gate level
• Intended as a modeling language for specification
and simulation
• Also used for synthesis
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Example of VHDL Description
VHDL Model of a 2input exclusive OR gate
entity XOR2_OP is
-- input output ports
port
(A, B : in BIT;
Z : out BIT);
-- Body
architecture EX_DISJUNCTION of
XOR_OP2 is
begin
Z <= A xor B;
end EX_DISJUNCTION;
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VHDL Entity Definitions
• A VHDL entity consists of two parts:
– interface denoted by keyword “entity”
– body denoted by keyword “architecture”
• Interface describes aspects visible outside
• Body describes how black box operates inside
• FORMAT:
entity identifier is
port (name: in / out / inout BIT/type);
end identifier;
-- lines beginning with two dashes are comments
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VHDL Architecture Body
• Architecture body describes how entity operates
• Allows for different implementations
• Can have behavioral or structural or mixed representations
FORMAT
architecture EX_DISJUNCTION of XOR_OP2 is
begin
Z <= A xor B;
end EX_DISJUNCTION;
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Architecture Body
• Body is divided into two parts
– Declarative part
– Statement part
architecture EX_DISJUNTION of XOR_OP2 is
-- declarative part
-- objects must be declared before they are used
begin
-- statement part
Z <= A xor B;
end EX_DISJUNCTION;
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Data Types in VHDL
• The type of a data object defines the set of values
that object can assume and set of operations on
those values
– VHDL is a strongly typed language
• Four classes of objects
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constants
variables
signals
files
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Constant Declaration
• The value of a constant cannot be changed
• FORMAT:
constant identifier {, } : subtype [ := expression]
• EXAMPLES:
constant number_of_bytes : integer := 4;
constant prop_delay : time := 3nsec;
constant e : real := 2.2172;
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Variable Declaration
• The value of a variable can be changed
• FORMAT
variable identifier {, ..} subtype [ := expression]
• EXAMPLES
variable index: integer := 0;
variable sum, average, largest : real;
variable start, finish : time : = 0 nsec;
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Variable Assignment Statement
• Once a variable is declared, its value can be
modified by an assignment statement
• FORMAT:
[ label : ] name := expression;
• EXAMPLES:
program_counter := 0;
index := index + 1;
• Variable assignment different from signal
assignment
– A variable assignment immediately overviews variable
with new value
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– A signal assignment schedules
value at later time
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Scalar Types
• Variable can only assign values of nominated type
• Default types
– “integer” , “real”, “character,” “boolean”, “bit”
• User defined types
– FORMAT:
type small_int is range 0 to 255;
• Enumerated type:
– FORMAT:
type logiclevel is (unknown, low, driven, high);
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Sub Types
• A type defines a set of values
• We can define a sub-type as a restricted set of
values from a base type
– FORMAT
subtype identifier is name range simple_expression
to/downto simple_expression
– EXAMPLE
subtype small_int is integer range -128 to 127;
subtype bit_index is integer range 31 downto 0;
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Attributes of Types
• A type defines a set of values and set of applicable
operations
• A predefined set of attributes are used to give
information about the values included in the type
• T’left = first (leftmost) value in T
• T’right = last (righmost) value in T
• T’value = the value in T that is represented by s
• EXAMPLES:
type set_index_range is range 21 downto 11;
set_index_range’left = 21
set_index_range’right = 11
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set_index_range’value(“20”)
= 2016
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Expressions and Operators
Operator
**
Abs
*, / , mod, rem
And, nand, or, nor, xor, xnor, not
Sll, srl, sla,sra
+, =, /=, <, <=, >, >=
Operation
Exponentiation
Absoluet value
Mul, div
Logical ops
Shift left/right
Add, subtract
Equal, greater
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Operand Types
Integer, real
numeric
Integer, real
Bit, boolean, or 1-D array
1-D array of bit/boolean
Integer, real
Scalar
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Sequential Statements
• Sequential statements of various types are
executed in sequence within each VHDL process
• Variable statement
variable := expression;
• If statement
• Case statement
• Loop statement
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If Statement
• FORMAT
if boolean_expression then
{sequential statement}
elsif boolean_expression then
{sequential statement}
else {sequential statement}
endif;
• EXAMPLE
if sel=0 then
result <= input_0; -- executed if sel = 0
else result <= input_1; -- executed if sel = 1
endif;
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Case Statement
• EXAMPLE of an ALU operation:
case func is
when pass1 =>
result := operand1;
when pass2 =>
result := operand2;
when add =>
result := operand1 + operand2;
when subtract =>
result := operand1 - operand2;
end case;
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Loop Statements
While condition loop
{sequential statements}
end loop;
while index > 0 loop
index := index -1;
end loop;
for identifier in range loop
{sequential statements}
end loop;
for count in 0 to 127 loop
count_out <= count;
wait for 5 ns;
end loop;
for i in 1 to 10 loop
count := count + 1;
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Concurrent Statements
• The concurrent statement in an architecture body
describe the module’s operation.
– Concurrency is useful in modeling the way real circuits
behave
architecture abstract of adder is
begin
add_a_b : process(a,b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
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Signal Declaration and Assignment
• Signal declaration: describes internal signal
signal identifier {…} : subtype [ := expression]
• EXAMPLE:
signal and_a, and_b : bit;
• Signal Assignment
name <= value_expression [ after time_expression];
• EXAMPLE
y <= not or_a_b after 5 ns;
• This specifies that signal y is to take on a new
value at a time 5 ns later statement execution.
• Difference from variable assignment:
– which only assigns some
values to a variable
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Concepts of Delays and Timing
• The time dimension in the signal assignment
refers to simulation time in a discrete event
simulation
• There is a simulation time clock
• When a signal assignment is executed, the delay
specified is added to current simulation time to
determine when new value is applied to signal
– Schedules a transaction for the signal at that time
output
input
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Specifying Technology Information
• One predefined physical type in VHDL: TIME
• Units: fs (10** -15 seconds), ps (1000 fs), ns, us,
ms, sec, min ( 60 sec), hr (60 min)
• User-defined physical types
type CAPACITANCE is range 0 to INTEGER’HIGH
units
fF;
-- Femtofarads
pF = 1000 fF;
-- Picofarads
nF = 1000 pF;
-- Nanofarads
end units
type VOLTAGE is range 0 to 2 ** 32 -1
units
uV;
-- Microvolt;
mV = 1000 uV;
V = 1000 mV;
end units;
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Specifying Delays
• Inertial Delay Model
– reflects physical inertia of physical systems
– glitches of very small duration not reflected in outputs
• SIG_OUT <= not SIG_IN after 7 nsec --implicit
• SIG_OUT <= inertial ( not SIG_IN after 7 nsec )
• Logic gates exhibit lowpass filtering
10ns
3 ns
SIG_IN
2ns
SIG_OUT
9 ns
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Transport Delays
• Under this model, ALL input signal changes are
reflected at the output
• SIG_OUT <= transport not SIG_IN after 7 ns;
10ns
3 ns
SIG_IN
2ns
SIG_OUT
9 ns
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19 ns
30 ns
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Example of Architecture Body
(AND_OR_INVERT)
architecture primitive of and_or_inv is
signal and_a, and_b, or_a_b : bit;
begin
and_gate_a : process (a1,a2) is
begin
and_a <= a1 and a2;
end process and_gate_a;
and_gate_b : process (b1,b2) is
begin
and_b <= b1 and b2;
or_gate: process (and_a, and_b) is
begin
or_a_b <= and_a or and_b;
end process or_gate;
inv : process (or_a_b) is
begin
y <= not or_a_b;
end process inv;
end architecture primitive;
a1
a2
y
end process and_gate_b;
b1
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Process Declaration of Clock Generator
Clock_gen: process (clk) is
begin
if clk = ‘0’ then
2*T_pw
clk <= ‘1’ after T_pw, ‘0’ after 2*T_pw;
endif;
end process clock_gen;
T_pw
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Process Generator for Multiplexer
mux: process (a, b, sel) is
a
begin
z
case sel is
when ‘0’ =>
b
z <= a after prop_delay;
sel
when ‘1’ =>
z <= b after prop_delay;
end process mux;
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Wait Statement
• A wait statement specifies how a process responds
to changes in signal values.
wait on signal_name
wait until boolean_expression
wait for time_expression
• Example on right shows process sensitivity list
EXAMPLE:
SAME AS:
half_add: process is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
wait on a, b;
end process;
half_add: process (a,b) is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
end process;
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Process Statement
• A process statement is a concurrent statement that
can be included in an architecture body to describe
all or part of the behavior of a module.
FORMAT:
process [ (signal_name, …) ] is
process_declarative item
begin
{ sequential statement;}
end process;
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Summary
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VHDL Language Basics
Interface
Architecture Body
Behavioral VHDL
Various Sequential Statements
Process Statements
Delay Models
NEXT LECTURE: VHDL Structural and Mixed
Description
• READING: Dewey 12.1, 12.2, 12.3, 12.4, 13.1,
13.2, 13.3. 13.4, 13.6, 13.7. 13.8
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