Transcript Architecture Design 1

Topics
•
Verilog register-transfer modeling:
– basics using traffic light controller;
– synthesis.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog
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•
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Verilog was designed as an efficient
simulation language.
Relatively simple, terse syntax.
Most popular HDL in use today.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog formulas
a&b
a|b
~a
a=b
a == b
#1
a <= b
Modern VLSI Design 4e: Chapter 8
Boolean AND
Boolean OR
Boolean NOT
Assignment
Equality
time
Concurrent
assignment
Copyright  2008 Wayne Wolf
Verilog constants
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Bit constant:
– 0, 1
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Bit vector constant:
– 4’b1010
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Some useful constructs
‘define aconst 2’b00
constant vector
$monitor($time,,”a=%b, b=%b”,a,b);
value monitor output
#1 a=0; b=0
#2 a=1; b=0
sequence of waveforms
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Four-valued OR function
0
1
X
z
0
0
1
x
x
1
1
1
1
1
X
x
1
x
x
Z
x
1
x
x
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Four-valued AND function
0
1
X
z
0
0
0
x
x
1
0
1
x
x
X
x
x
x
x
Z
x
x
x
x
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog structural model
Module adder(a,b,cin,sum,cout);
input a, b, cin;
Time delay for output
output sum, cout;
xor #2 s(sum,a,b,cin); // sum
and #1 // carry out
c1(x1,a,b); c2(x2,a,cin);
Output
c3(x3,b,cin);
wire
Input wires
or #1
c4(cout,x1,x2,x3);
endmodule
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
If statements
if (b | c) then
y = 1;
else
y <= 0;
y assigned value
in both cases
Modern VLSI Design 4e: Chapter 8
if (b | c) then
y = 1;
else
z = a | b;
different net assigned
in true, false cases
Copyright  2008 Wayne Wolf
Conditional assignments
if (b | c) then
y = ‘1’;
else
z = a | b;
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Simulation:
– Condition is tested
based on current signal
states.
– Only one net gets an
event.
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Synthesis:
– Creates don’t-cares for
y and z.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Loop statement
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A loop performs an operation over an array
of signals:
for (i=0; i<N; i=i+1)
x[i] = a[i] & b[i];
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
always statement
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always guards execution of a block of
statements.
– Block is always executed on the logical
condition.
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always @(sigval) begin
end
Modern VLSI Design 4e: Chapter 8
..
Copyright  2008 Wayne Wolf
Structure of a Verilog model
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Module statement.
– Declares I/O pin names.
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Declarations:
– inputs and outputs;
– registers.
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Body.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
A synthesizable Verilog
archtiecture
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Declarations of pins and registers.
Definitions of constants (similar to C
#define statement).
– ‘define GREEN ‘2b11
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Combinational and sequential portions.
– Within @always statements.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog combinational portion
always @(ctrl_state or short or long or
cars) begin
when HG: begin // state hwy-green
highway_light = GREEN;
farm_light = RED;
if (cars & long) then
begin ctrl_next = HY; start_timer =
1; end
else begin ctrl_next - HG;
start_timer = 0; end
end
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog sequential portion
always @(posedge clock or negedge reset)
if (~reset)
ctrl_state <= 0;
else
ctrl_state <= ctrl_next;
end
Condition on clock/reset
Transfer of next state
to current state
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Testbench structure
Unit under test
(UUT)
tester
testbench
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Verilog testbed organization
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Module declaration.
– Two components: UUT and tester.
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•
Definition of UUT.
Definition of tester.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Testbench tester process
initial
Prints signal values
begin
$monitor($time,,”a=%b”,a);
#1 a=0; b=0; cin=0;
#1 a=1; b=0; cin=0;
Test inputs
#2 a=1; b=1; cin=1;
end
endmodule
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf