Transcript Document
Photo taken at Sra Patum Palace
SUT is a full member of ALICE
Memorandum of Understanding between SUT and ALICE.
SUT-TMEC-SLRI-NECTEC Thailand 2013 18 SUT Simulation and reconstruction software Physics Performance SLRI Characterization of prototype pixel chips using 1 GeV electron beam TMEC Participation in microelectronics design and packaging activities NECTEC Tier 2 Grid site, Online-Offline operation
SUT now participation in ITS upgrade
Performance Developing Geometry (beampipe and staves) for AliRoot which will be used in the Simulation and Reconstruction Software of the new Inner Tracking System (ITS) at ALICE"
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Thai Microelectronics Center (TMEC) in the ALICE ITS Resistance (SRP) measurements carried out Profile are on
10 9
epitaxial silicon wafers are carried
20.24%µm%
out at TMEC before CMOS processing.
10 8 10 7 10 6 10 5 10 4 10 3 10 2 0 C2_after calibration C2_before calibration 5 10 15 20 Depth [um] 25 30 35 6
NECTEC and ALICE Grid site at SUT
Collaborate with National Electronics and Computer Technology Center (NECTEC) to setup a Grid site for ALICE@SUT as part of the Thailand National e-Science Infrastructure Consortium 336 Cores IBM x3755 M3 100 TB IBM DCS 3700
Sensor characterization, assembly and test Working together with the Synchrotron Light Research Institute (SLRI) to setup an ITS test system for the characterization of pixel sensors with laser beams, radioactive sources and test beam in Thailand
Future Plan
SUT: physics analysis TMEC: silicon microchannel cooling of the sensor, Thinning and dicing SLRI: assembly and test the complete sensor module NECTEC: WLCG GRID and online offline data treatment