Transcript Test Architecture Design and Optimization for Three

Test Architecture Design and
Optimization for ThreeDimensional SoCs
Li Jiang, Lin Huang and Qiang Xu
CUhk Reliable Computing Laboratry
Department of Computer Science & Engineering
The Chinese University of Hong Kong
Outline
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Introduction
Motivation
Proposed approach
Experiments
Conclusion
Introduction
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3D technique
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Vertically stack dices
TSV as interconnect
TSV
Device
Layer
Cu
Cu
Bond Pad
Benefit of 3D IC
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Bulk Si
Interconnect
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Performance, Power, Area
Memory bandwidth
Heterogeneous technology
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3D SoCs
Metal
Device
Layer
Layer 1
TSV
Layer 2
Bonding Methods in 3D Technology
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W2W bonding
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Bond->Cut->Package Test
Low yield
D2D/D2W bonding
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Utilize pre-bond test
Test->Cut->Bond
Only stack KGD
Motivation
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Traditional SoC test architecture optimization
TAM1
TAM2
TAM3
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5
1
2
3
4
6
Post-Bond Test
3D SoC test architecture optimization
TAM11
TAM
22
Empty
Empty
55
5
33
11
22
Idle
Idle
33
Idle
Idle
TAM22
TAM
11
TAM33
TAM
Empty
44
66
66
Empty
44
Layer11
3DChip
Chip
Layer
Layer 2
3D
Pre-Bond
Test
Post-Bond
Test
Pre-Bond Test
Post-Bond Test
After
Move
Move 1 bit from
TAM
3 to TAM 2
Problem Definition
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Given
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Set of cores, Test Parameters, Position
Available TAM width
Determine
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Number of TAM
Core assignment
Width of each TAM
Objective
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Minimize the total test cost
CTotal = CTest-Time * α+ CWire-Length *(1- α)
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CTest-Time = C3DChip + Σ CLayer
CWire-Length depends on routing model
Routing Model
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TAM for post-bond test
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TAM segments for pre-bond test
Additional test pad
TSV linking segments together
Routing cost model
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2
1
Wire length:
TAM2
Layer 1
5
Wrapper
TAM1
TSV
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Manhattan distance
between core centers
Neglect length of TSV
Wire length * TAM width
Layer 2
TAM3
6
4
3
2'
TAM2
Approach
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Simulated annealing
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Appropriate for this scale
Solution representation
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Core assignment & TAM width
Move
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Move core
Change TAM width
Large solution space
Proposed approach
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Outer SA-based core assignment
Inner TAM width distribution heuristic
(Core1,Core2) ,(Core5,Core7,Core8)
TamWidth1,TamWidth2
(Core1,Core2,Core5) ,(Core7,Core8)
TamWidth1,TamWidth2
(Core1,Core2) ,(Core5,Core7,Core8)
Heuristic
TamWidth1,TamWidth2
(Core1,Core2,Core5) ,(Core7,Core8)
Heuristic
TamWidth1,TamWidth2
Approach
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Overflow
Initial Solution
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Outer SA-based core assignment
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Redundancy in representation
Move
Inner TAM Width
Distribution Heuristic
(C1,C3),(C2,C4,C5)
Record Cost
(C3,C1),(C2,C4,C5)
Check Temperature
Rules to eliminate redundancy
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1-to-1 corresponding between
representation and solution
Prove of completeness
Check Temperature
Approach
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Greedy inner TAM width allocation procedure
Assign 1 bit to each TAM
Set b = 1
b = b+1
Find a TAM Brings the Min Cost
Record Test Cost
No
Whether can Reduce Test Cost?
Yes
TAM Width=0?
Yes
Stop
Experiment Setup
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Baseline algorithms
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TR-1:
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Apply existing optimization algorithm to the 3D SoC layer by layer
Adjust the TAM width among layers iteratively
Optimize the pre-bond test architecture
TR-2:
• Apply existing optimization algorithm to the whole 3D chip
• Optimize the post-bond test architecture
Benchmark: ITC02 SoC benchmark
Map to 3D SoC
Previous wrapper optimization algorithm
Testbus as TAM
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Time,TR-1
Time,SA
WL,TR-2
50
Time,TR-2
WL,TR-1
WL,SA
40
Thousands
Testing Time on p22810
30
20
10
0
16
24
32
48
40
TAM Width
56
64
Wile Length
Test Time
Millions
Experimental Results
80
70
Testing Time
60
12500
a=0.6,t512505
Time,TR-2
Time,SA
WL,TR-2
WL,SA
10500
8500
50
6500
40
4500
30
2500
20
500
10
0
-1500
16
24
32
40
48
TAM Width
56
64
Wire Length
Millions
Experimental Results
80
70
60
Time,TR-2
Time,SA
WL,TR-2
WL,SA
12500
a=0.4,t512505
10500
8500
50
6500
40
4500
30
2500
20
500
10
0
-1500
16
24
32
40
TAM Width
48
56
64
Wire Length
Testing Time
Millions
Experimental Results
Conclusion
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Focus on D2D/D2W
Pre-bond test and post-bond test
Proposed efficient and effective approach can
optimize the 3D Test Architecture
To reduce the solution space, we split Simulated
Annealing based approach into two part
Experimental results show the efficiency of proposed
approach
Thank You
Q&A