Transcript 嵌入式系统架构软体设计 - :+: 德霖技術學院

嵌入式系统架构软体设计
嵌入式系統架構軟體設計
---using ARM
Day #3,#4,#5 Modules Outline
嵌入式系統架構軟體設計
---using ARM
 Day #3
 Simple RISC Assembly Language
 ARM Assembly Language
 ARM Development Suite 使用練習
 Day #4
 Arm Instruction set
 Important ASM Programming Skills
 ARM/THUMB/C Interworking
 Day #5
 ARM Exception Handler
 Build ARM ROM Image
 Use NET-Start! ucLinux BSP
課程介紹
嵌入式系統架構軟體設計
---using ARM
嵌入式系統產品設計流程概觀
嵌入式系統架構軟體設計
---using ARM
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Steve Furber, ARM system-on-chip Architecture, 2nd ed.
Seal, ARM architecture reference manual, 2nd ed.
ARM Development Suite-Getting Started
ARM Development Suite-Developer Guide
ARM Development Suite-Assembler Guide
http://www.uclinux.org/
2002嵌入式系統開發經驗
Building powerful platform with Windows CE
Software Engineering, A practitioner’s Approach 3rd ed.
Professional Symbian Programming
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #3-1: Simple RISC Assembly Concept
嵌入式系統架構軟體設計
---using ARM
RISC精简指令集vs.CISC复杂指令集
RISC (e.g. ARM)
CISC (e.g. x86)
Hardware instruction decode logic
Large microcode ROMs to decode
instruction
Pipeline execution
Allow little pipeline
Single -cycle execution
Many cycles to completer a single
instruction
Fetch
A smaller die size
A shorter development time
A higher performance
Poor code density
Decode Register ALU
Fetch
MEM
Decode Register ALU
Fetch
Write
MEM
Decode Register ALU
Fetch
Write
MEM
Write
Decode Register ALU
MEM
Write
Clock
嵌入式系統架構軟體設計
---using ARM
MUO 一個簡單的處理器
Addre s s bus
硬體單元
PC
ACC
ALU
IR
功能
Program Counter
Accumulator
Arithmetic logic unit
Instruction register
Control
PC
ACC
ALU
Data bus
IR
MEM
嵌入式系統架構軟體設計
---using ARM
指令規則
Opcode
4 bits
MUO指令集與資料路徑
S
12 bits
Addre s s bus
指令
Opcode
功能
LDA S
0000
ACC=mem[S]
STO S
0001
mem[S]=ACC
ADD S
0010
ACC=ACC+mem[S]
SUB S
0011
ACC=ACC-mem[S]
JMP S
0100
PC=S
JGE S
0101
If ACC>= PC=S
JNE S
0110
If ACC!=0 PC=S
STP
0111
stop
Control
PC
ACC
ALU
Data bus
IR
MEM
嵌入式系統架構軟體設計
---using ARM
指令執行範例
ADD 0x16A
ACC:=ACC+mem[0x16A]
Addre s s bus
Control
PC
ACC
ALU
Data bus
IR
MEM
嵌入式系統架構軟體設計
---using ARM
C function:
Main()
{
C=A+B;
}
運算範例
Addre s s bus
Control
PC
0x100
0x104
IR
0x108
ACC
A
B
C
MEM
ALU
Data bus
MUO 機器指令
LDA
ADD
STO
0x100
0x104
0x108
指令
Opcode
功能
LDA S
0000
ACC=mem[S]
STO S
0001
mem[S]=ACC
ADD S
0010
ACC=ACC+mem[S]
SUB S
0011
ACC=ACC-mem[S]
JMP S
0100
PC=S
JGE S
0101
If ACC>= PC=S
JNE S
0110
If ACC!=0 PC=S
STP
0111
stop
嵌入式系統架構軟體設計
---using ARM
練習： MUO微處理器的運算
Addre s s bus
0x000
0x002
0x004
0x006
0x008
LDA 0x100
SUB 0x104
STO 0x100
JNE 0x000
STP
Control
PC
0x000
0x002
0x004
0x006
IR
ACC
MEM
ALU
0x100
0x104
0x108
11
12
13
14
100
10
Data bus
請描述此段程式的動作，暫存器值的變化、
與資料流。請用C語言來寫出這段程式碼。
指令
Opcode
功能
LDA S
0000
ACC=mem[S]
STO S
0001
mem[S]=ACC
ADD S
0010
ACC=ACC+mem[S]
SUB S
0011
ACC=ACC-mem[S]
JMP S
0100
PC=S
JGE S
0101
If ACC>= PC=S
JNE S
0110
If ACC!=0 PC=S
STP
0111
stop
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #3-2: ARM Assembly Language
嵌入式系統架構軟體設計
---using ARM
ARM7TDMI資料流
ABE A[31:0]
Adress Incrementer
Address Register
e.g.r3:=r4+(r4,,2)
ADD r3,r4,r4,LSL#2
incrementer
PC
A bus B bus
PC Update
Register Bank
A
L
U
Decode Stage
A
B
instruction
Decompression
Multiplier
B
U
S
Introduction
Decoder
B
U
S
Barrel
Shifter
B
U
S
and
ISYNC
nIRQ
nFIQ
nRESET
ABORT
nTRANS
nMREQ
SEQ
LOCK
nM[4:0]
Read Data
Rigister
Write Date
Register
Control
Logic
32 Bit ALU
DBE
BIGENO
MCLK
nWAIT
nRW
MAS[1:0]
D[31:0]
nOPC
nCPI
CPA
CPB
嵌入式系統架構軟體設計
---using ARM
ARM 的暫存器
r0
r1
r2
r3
r4

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

r5
r6
r7
30 general-purpose, 32 bits registers
1 Program Counter (PC)
1 Current Program Status Register (CPSR)
5 Saved Program Status Registers (SPSR)
r8
r8_f iq
r9
r9_f iq
r10
r10_f iq
r11
r11_f iq
r12
r12_f iq
r13 (sp)
r13_f iq
r13_irq
r13_sv c
r13_abt
r13_und
r14 (lr)
r14_f iq
r14_irq
r14_sv c
r14_abt
r14_und
spsr_f iq
spsr_f iq
spsr_f iq
r15 (pc)
cpsr
User mode
FIQ mode
irq mode
SVC mode
spsr_abt
abort mode
spsr_und
undefined mode
嵌入式系統架構軟體設計
---using ARM
Program Status Register
 CPSR: Current Program Status Register
 SPSR: Saved Program Status Register
 Condition code flags
 N: Negative result from ALU
 Z: Zero result from ALU
 C: ALU operation Carried out
 V: ALU operation overflowed
31 30 29 28 27
24
N Z C V
J
Q
 Interrupt Disable bits
 I: disable the IRQ
 F: Disable the FIQ
undefined
 T bit
 Architecture xT only
 T=0: ARM state
 T=1: Thumb state
7 6 5
4
I F T
mode
 Q: Sticky Overflow flag
 Architecture 5TE only
 QADD, QSUB…
0
Mode bits
J: Processor in Jazelle state
Architecture 5TEJ only
Specify the processor mode
10000 User
10001 FIQ
10010 IRQ
10011 SVC
10111 Abort
11011 Undef
11111 System
嵌入式系統架構軟體設計
---using ARM
Program Counter –R15
 ARM state:
 All ARM instructions are four bytes long (one 32-bit word) and are always
aligned on a word boundary.
 The PC value is stored in bits [31:2] with bits [1:0] undefined.
 In Thumb state:
 All instructions are 16 bits wide, and halfword aligned
 The PC value is stored in bits[31:1] with bits [0] undefined.
 In Jazelle state:
 All instructions are 8 bits wide.
 The processor performs a word access to read 4 instructions at once.
嵌入式系統架構軟體設計
---using ARM
Link Register –R14
 Register 14 is the Link Register (LR).
 This register holds the address of the next instruction after a Branch and Link
(BL) instruction, which is the instruction used to make a subroutine call.
 At all other times, R14 can be used as a general-purpose register
嵌入式系統架構軟體設計
---using ARM
Other Register R0-R13
 The remaining 15 registers have no special hardware purpose.
 Their uses are defined purely by software.
 By convention, ARM assembly language use R13 as Stack Pointer.
 C and C++ compilers always use R14 as the Stack Pointer(SP).
嵌入式系統架構軟體設計
---using ARM
Structure of ARM Assembly Language Module
AREA Sectionname{,attr}{,attr}…
Start of New code or data section.
CODE: contain machine instructions.
READONLY: section should not be written to.
Other attr: DATA, NOINIT, READWRITE,…
Declares an entry point to a program.
; C:\ARM \ADSv1_2\Exam ple\asm \arm ex.s
;
AREA ARM ex, CODE, READONLY
ENTRY
start
M OV r0, #10
M OV r1, #3
ADD r0, r0, r1
stop
Labels.
M OV r0, #0x18
LDR r1, =0x20026
SWI 0x123456
END
Declares the end of the source file.
嵌入式系統架構軟體設計
---using ARM
Calling Subroutines Uses BL
 BL destination
• destination is the label on the first instruction of the subroutine.
 BL does:
• place the return address in the link register (R14)
• sets PC to the address of the subroutine.
 In the subroutine
• we can use “MOV pc,lr” to return.
 By convention, R0-R3 are used to pass parameters.
嵌入式系統架構軟體設計
---using ARM
; C:\ARM\ADSv1_2\Example\asm\subrout.s
;
AREA subrout, CODE, READONLY
ENTRY
start
MOV r0, #10
MOV r1, #3
BL
doadd
Calling Subroutines Example
; name this block of code
; mark first instruction
; to execute
; Set up parameters
; Call subroutine
stop
MOV
LDR
SWI
r0, #0x18
r1, =0x20026
0x123456
doadd
ADD r0, r0, r1
MOV
pc, lr
END
; angel_SWI reason_report Exception
; ADP_Stopped_ApplicationExit
; ARM semihosting SWI
; Subroutine code
; Return from subroutine.
; Mark end of file
嵌入式系統架構軟體設計
---using ARM
Constant Data Types
 Numbers Numeric constants are accepted in three forms:
• Decimal, for example, 123
• Hexadecimal, for example, 0x7B
• n_XXX where:
• n is as base between 2 and 9
• xxx is a number in that base.
 Boolean TRUE and FALSE must be written as {TRUE} and {FALSE}.
 Characters constants consist of opening and closing single quotes ‘X’,
enclosing either a single character or an escaped character, using the standard
C escape characters.
 Strings consist of opening and closing double quotes “XXXX”. If double
quotes or dollar signs are used within a string as literal text characters, they
must be represented by a pair of the appropriate character.
 For example, you must use $$ if you require a single $ in the string. The
standard C escape sequences can be used within string constants.
嵌入式系統架構軟體設計
---using ARM
Conditional ARM Instructions
 Almost all ARM instructions can be conditionally executed.
e.g.
ADDS
ADDEQ
r0, r1, r2
r0, r1, r2
 Execute if the N, Z, C and V flags in the CPSR satisfy a condition specified
in the instruction, otherwise, NOP.
指令名稱
XXXCC
條件
嵌入式系統架構軟體設計
---using ARM
Conditional Execution
 Almost every ARM instruction can be executed conditionally on the state of the
ALU state flags in the CPSR.
 Add an S suffix to an ARM data processing instruction to make it update the ALU
state flags in the CPSR
 E.g. ADDS r0, r1, r2 ; r0= r1+ r2 and update ALU status in CPSR.
 In ARM state, you can:
 update the ALU status flags in the PSR on the result of a data operation
 execute several other data operation without updating the flags
 execute following instructions or not, according to the state of the flags
updated in the first operation.
 In Thumb state
 most data operations always update the flags
 and conditional execution can only be achieved using the conditional branch
instruction (B).
 Do not use the S suffix with CMP, CMN, TST, or TEQ. These comparison
instructions always update the flags.
嵌入式系統架構軟體設計
---using ARM
ALU Status Register in CPSR
 N Set when the result of the operation was Negative.
 Z Set when the result of the operation was Zero.
 C when the result of the operation was Carry.
 A carry occurs if the result of an addition is greater than or equal to 232
 If the result of a instruction is positive,
 or as the result of an inline barrel shifter operation in a move or logical
instruction.
 V Set when the operation caused oVerflow.
 Overflow occurs if the result of an add, subtract, or compare is greater
than or equal to 231, or less than – 231.
 Q ARM architecture v5Eonly. Sticky flag.
 Used to detect saturation in special saturating arithmetic instructions (e.g.
QAD, ASUB, QDADD, and QDSUB),
 Or overflow in certain multiply instructions (SMLAxy and SMLAWy)
嵌入式系統架構軟體設計
---using ARM
Suffix
EQ
NE
CS/HS
CC/LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Flags
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C set or Z clear
N and V the same
N and V differ
Z clear, N and V the same
Z set, N and V differ
Any always
Conditional Code Suffixes
Meaning
Branch Example
Equal
BEQ
Not equal
BNE
Highter or same (unsigned >=)BCS
Lower (unsigned <)
BCC
set Negative or Minus
BMI
Positive or zero
BPL
Overflow
BVS
clear No overfloew
BVC
Higher (unsigned>)
BHI
Low or the same (unsigned <=)BLS
Signed>=
BGE
Signed<
BLT
Signed>
BGT
Signed<=
BLE
This suffix is normally omittedBAL
嵌入式系統架構軟體設計
---using ARM




ADD r0, r1, r2
ADDS r0, r1, r2
ADDCSS r0, r1, r2
CMP r0, r1
Conditional Code Examples
;r0 = r1 + r2, don’t update flags
;r0 = r1 + r2, and update flags
;if C flag set then r0 = r1 + r2, and update flags
;update flags based on r0-r1.
 Example code sequence:
MOV R0, #0
LOOP ADD R0, R0, #1
CMP R0, #10
BNE LOOP
SUB R1, R1, R0
R0=0
R0=R0=+1
R0==10?
Ye s
R1=R1-R0
No
Write Efficient and small size Code by
Conditional Instruction
嵌入式系統架構軟體設計
---using ARM
If (r0!=5)
{
r1=r1+r0-r2;
}
CMP
BEQ
ADD
SUB
PASS .....
.....
r0, #5
PASS
r1,r1,r0
r1,r1,r2
CMP
ADDNE
SUBNE
r0, #5
r1,r1,r0
r1,r1,r2
嵌入式系統架構軟體設計
---using ARM
Exercise
Write program by ARM assembly, & evaluate the execution cost in clock.
A Branch needs 3 cycles, others cost 1.
註：唯需透過CMP, SUB, B這
三個指令，加上條件式， 就
可以完成。
Start
r1=r2?
Ye s
Stop
c
r1>r2?
Ye s
r1=r1-r2
No
r1=r2-r1
While (r1!=r2) do
{
if (r1>r2)
r1=r1-r2;
else
r2=r2-r1;
}
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #3-3: ARM Development Suite使用練習
嵌入式系統架構軟體設計
---using ARM
armcc&tcc
armcpp&tcpp
armasm
armlink
CodeWarrior
AXD
fromelf
armar
ARMulator
ARM ADS 1.2
ANSI C compilers
ISO/Embedded C++ compiler
ARM/Thumb assembler
Linker
Windows IDE
Debugger
Format converter
Librian
Instruction set simulator
Others:
 C & C++ Libraries
 ARM firmware suite
 AM application library
 RealMonitor: for real time debug monitor
嵌入式系統架構軟體設計
---using ARM
Implementation Integration
by command line, makefile, CodeWarrior
ASM source
Modules
Libraries
.s
armasm
C source
Modules
.o
armlink
ELF/ DWARF2
image
ELF object files
With DWARD2
Debug tables
fromelf
.c
¡ñ
armcc / tcc
.o
fromelf
¡ñ
¡ñ
¡ñ
Disassembly
Code size
Data size
...
C++ source
Modules
ROM
image
.cpp
armcpp / tcpp
.o
armar
Libraries
嵌入式系統架構軟體設計
---using ARM
Pre-configured Project Stationary Files
 Debug
 This build target is configured to built output binaries that are fully
debuggable, at the expense of optimization.
 Release
 This build target is configured to output binaries that are fully optimized,
at the expense of debug information.
 DebugRel
 This build target is configured to build output binaries that provide
adequate optimization, and give a good debug view.
嵌入式系統架構軟體設計
---using ARM
Possible Development Environments
Print port
JTAG
Multi ICE
Host Computer
Angel
Serial,
Ethernet
Debugger
ELF/DWARF2 image
Serial,
Ethernet
ARMulator
Insruction Set Simulation
Target board
嵌入式系統架構軟體設計
---using ARM
 ARM Developer Suite Version 1.2 Getting Started
 請依Chapter 3練習使用ADS。
Reference
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #3-4: ARM Instruction Set
嵌入式系統架構軟體設計
---using ARM
 所有指令為32 bits
 ADD r0, r1, r2;
r0:=r1+r2
 大部分的指令，可以在一個週期內執行完成
 指令皆可為有條件式執行
 Load/store架構
ARM 指令集特點
嵌入式系統架構軟體設計
---using ARM
 Thumb指令長度為16 bits
 針對程式碼的密度最佳化， 約為65%的ARM code size
 適合小記憶體系統
 Thumb指令支援的功能為ARM指令集的一部分
 執行期間必須切換到Thumb模式
ADDS r1,r1,#3
ADD
r1,#3
Thumb指令集
嵌入式系統架構軟體設計
---using ARM
Jazelle
 Jazelle技術可以讓ARM執行8-bit Java Bytecode
 硬體可以支援到95%的bytecodes
 速度約為一般軟體JVM的五倍
ARM
Instruction
Stream
Thumb
Jazelle
Execution
Unit
嵌入式系統架構軟體設計
---using ARM
 Branch instructions
 Data-processing instructions
 Load and store instructions
 Status register transfer instructions
 Coprocessor instructions
 Exception-generating instructions.
ARM指令集分類
嵌入式系統架構軟體設計
---using ARM
 B Branch
 BL Branch with link
 Store the return address to r14
 e.g.
CMP r2, #0
BLEQ function
…
function
…
MOV PC, r14
Branch Instructions
PC=0x1200
0x2200
B 0x2200
嵌入式系統架構軟體設計
---using ARM
Branch Instruction Encoding
Assembly Format:
B{L}{<cond>}{S}
B{L}{<cond>}{S}
Rm
<Target address>
Branch and branch with link binary encoding
31
28 27
25 24 23
cond 1 0 1 L
0
24-bit signed word offset
 The range of the branch instruction is +/- 32 Mbytes
 ‘L’: the branch and link variant.
嵌入式系統架構軟體設計
---using ARM
 e.g. C
if (a=0) function 1 (1);
Else…
c
function 1(){
function2();
…}
function2(){
return;}
Branch instructions example
ASM
function 1
STMFD
BL
…
LDMFD
function2
…
MOV
r13!, {r0-r4, r14}
function2
r13!, {r0-r4, pc}
pc, r14
嵌入式系統架構軟體設計
---using ARM
Data-processing Instructions Encoding
Assembly Format:
<op>{<cond>}{S} Rd, Rn,#<32-bit immediate>
<op>{<cond>}{S} Rd, Rn,Rm, {shift}
31
cond
28 27 26 25 24
Arithmetic/logic function
Set condition codes (NZVC)
First operand register
Destination register
21 20 19
# opcode S
0 0
12 11
16 15
Rn
0
Rd
Operand 2
11
8
#rot
1
0
7
8-bit immediate
Immediate alignment
11
0
#shift Sh 0
Immediate shift length
11
0
7 6 5 4 3
shift type
Rm
Second operand register
8 7 6 5 4 3
Rs
Register shift length
0 Sh 1
0
Rm
嵌入式系統架構軟體設計
---using ARM
Data Processing Opcode
Assembly Format:
<op>{<cond>}{S}
<op>{<cond>}{S}
Opcode Mnemonic
[24:21]
Rd, Rn #<32-bit immediate>
Rd, Rn, Rm, {<shift>}
Meaning
Effect
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Logical bit-wise AND
Logical bit-wise excusive OR
Subtract
Reverse subtract
Add
Add with carry
Subtract with carry
Reverse subtract with carry
Test
Test equivalence
Compare
Compare negated
Logical bit-wise OR
Move
Bit clear
Move negated
AND
EOR
SUB
RSB
ADD
ADC
SBC
RSC
TST
TEQ
CMP
CMN
ORR
MOV
BIC
MVN
Rd:=Rn & Op2
Rd:=Rn EOR Op2
Rd:=Rn-Op2
Rd:=Op2-Rn
Rd:=Rn+Op2
Rd:=Rn+Op2+C
Rd:=Rn-Op2+C-1
Rd:= Op2-Rn+C-1
Scc on Rn&Op2
Scc on Rn EOR Op2
Scc on Rn-Op2
Scc on Rn+Op2
Rd:=Rn | Op2
Rd:=Op2
Rd:=Rn AND NOT Op2
Rd:=NOT Op2
嵌入式系統架構軟體設計
---using ARM
Example Data-processing Instructions
 Arithmetic operations
 ADD
r0,r1,r2
 SUB
r0,r1,r2
 RSB
r0,r1,r2
; r0=r1+r2
; r0=r1-r2
; r0=r2-r1
 Bit-wise logical operations
 AND
r0,r1,r2
 ORR
r0,r1,r2
 EOR
r0,r1,r2
 BIC
r0,r1,r2
; r0 = r1&r2
; r0 = r1| r2
; r0 = r1 xor r2
; r0 = and not r2; bit clear
嵌入式系統架構軟體設計
---using ARM
Example Data-processing Instructions (cont.)
 Register movement operations
 MOV
r0,r2
; r0=r2
 MVN
r0,r2
; r0=not r2
 Comparison operations (set condition code bits N, Z, C, V)
 CMP
r1,r2
; set cc on r1-r2
 Immediate operands
 ADD
r3,r3,#1
 AND
r8,r7, #&ff
 & : base 16
; r3=r3+1
; r8=r7[7:0]
嵌入式系統架構軟體設計
---using ARM
Shifter
Destination
 LSL: Logical Left Shift (X2)
 ASR: Arithmetic Right Shift
0
 LSR: Logical Shift Right (/2)
Destination
Destination
Preserve Sign bit
 ROR: Rotate Right
Destination
0
嵌入式系統架構軟體設計
---using ARM
e.g. #1
ADD r3,r2,r1, LSL #3;

r3:= r2+8*r1
e.g. #2
r0=r1*5
 r0=r1+(r1*4)
 ADD r0 ,r1, r1, LSL #2
Shifter Applications
嵌入式系統架構軟體設計
---using ARM
Multiply Instruction Binary Encoding
Assembly Format
MUL{<cond>}{S} Rd, Rm, Rs
MLA{<cond>}{S} Rd, Rm, Rs, Rn
<mul>{<cond>}{S} RdHi, RdLo, Rm, Rs
31
cond
28 27
24 23
0000
21 20 19
mul
16 15
12 11
S Rd/RdHi Rn/RdLo
8 7
Rs
4 3
1 0 0 1 Rm
RdHi: the most significant 32 bits of 64-bit format number
RdLo: the least significant 32 bits of 64-bit format number
Meaning
0
Opcode
[23:21]
000
001
Mnemonic
Effect
MUL
MLA
Multiply (32-bit result)
Multiply-accumulate (32-bit result)
Rd:=(Rm*Rs)[31:0]
Rd:=(Rm*Rs+Rn)[31:0]
100
101
UMULL
UMLAL
Unsigned multiply long
Unsigned multiply-accumulate long
RdHi:RdLo:=Rm*Rs
RdHi:RdLo+=Rm*Rs
110
111
SMULL
SMLAL
Signed multiply long
Signed multiply-accumulate long
RdHi:RdLo:=Rm*Rs
RdHi:RdLo+=Rm*Rs
嵌入式系統架構軟體設計
---using ARM
Count Leading Zeros Instruction (v5T only)
Assembly Format:
CLZ{<cond>}{S} Rd, Rm
31
cond
28 27
16 15
0 0 0 1 01 1 0 0
0
0
destination register
0 Rd
12 11
4 3
0
0 0 0 0 0 0 0 1 Rm
source register
 Sets Rd to the number of the bit position of the most significant 1 in Rm. If
Rm=0 Rd=32.
 E.g.
MOV
r0, #&100
CLZ
r1, R0
r1=8
嵌入式系統架構軟體設計
---using ARM
練習
 用ARM Assembly寫一個程式，包含一個subroutine用來做x10的運算。
 用ADS環境。
 不支援具有乘法器功能的ARM Core 。
main()
{
x=5;
y=mul_ten(x);
}
int mul_ten(x)
{
return 10*x;
}
嵌入式系統架構軟體設計
---using ARM
Assemble Format:
LDR|STR{<cond>}{B}
LDR|STR{<cond>}{B}
LDR|STR{<cond>}{B}
31
Single Word and Unsigned Byte Data Transfer
Instruction Binary Encoding
Rd,[Rn, <offset>]{!}
Rd,[Rn], <offset>
Rd,LABEL
28 27 26 25 24 23 22 21 20 19
0 1
# P U B W L
cond
16 15
Rn
; Pre-indexed form
; Post-indexed form
; PC-relative form
12 11
0
offset
Rd
source/destination register
base register
load/store
write-back (auto-index)
unsigned byte/word
up/down
pre-/post-index
25
0
11
0
12-bit immediate
25
11
1
#shift
immediate shift length
shift type
of fset register
7
6 5
4 3
Sh
0
Rm
0
嵌入式系統架構軟體設計
---using ARM
 Single register load and store
LDR
r0, [r1]
STR
r0, [r1]
 Base plus offset addressing
 Pre-indexing
LDR
r0, [r1, #4]
 Auto indexing
LDR
r0, [r1, #4]!
 Post-indexed
LDR
r0, [r1], #4
 PC-relative
LDR
STRB
…
UART_ADD &
Load and Store Examples
; r0 := mem32[r1]
; mem32[r1] := r0
; r0 := mem32[r1+4]
; r0 := mem32[r1+4], r1=r1+4
; r0 := mem32[r1], r1=r1+4
r1, UART_ADD
r0, [r1]
; UART address into r1
; store data to UART
&10000000
; address literal
嵌入式系統架構軟體設計
---using ARM
Assemble Format:
LDR|STR{<cond>}H |SH|SB
LDR|STR{<cond>}H |SH|SB
31
Half-word and Signed Byte Data Transfer
Instruction Binary Encoding
Rd;[Rn, <offset>]{!} ; Pre-indexed form
Rd;[Rn], <offset>
; Post-indexed form
28 27 26 25 24 23 22 21 20 19
0 0 0 P U # W L
cond
16 15
Rn
12 11
Rd
8 7
1
offsetH
6 5 4 3
0
S H 1 offsetL
source/destination register
base register
S
H
Data type
1
0
Signed byte
load/store
write-back (auto-index)
0
1
Unsignedhalf-word
up/down
1
1
Signedhalf-word
pre-/post-index
22
11
Imm[7:4]
1
• An unsigned value is zeroextended to 32 bits when
loaded;
• A singed value is extended
to 32 bits by replicating the
most significant bit of the data.
8
11
22
0 0 0 0
0
offset register
8
3
8
Imm[3:0]
3
8
Rm
嵌入式系統架構軟體設計
---using ARM
ADR
ADR
ADR
LOOP LDRSH
STR
CMP
BLT
r1, ARRAY1
r2, ARRAY2
r3, ENDARR1
r0, [r1], #2
r0, [r2], #4
r1, r3
LOOP
Half-word Load/Store Example
; half-word array start
; word array start
; ARRAY1 end +2
; get signed half-word
; save word
; check for end of array
; if not finished, loop
嵌入式系統架構軟體設計
---using ARM
練習：字串複製
 寫一個Assembly程式做字串複製的動作。
 用ADS環境。
A=“Hello, this is a sunny day!”
B=“
”
嵌入式系統架構軟體設計
---using ARM
Multiple Register Data Transfer Instruction
Binary Encoding
Assembly Format:
LDM|STM{<cond>}<add mode> Rn{!}, <registers>
31
28 27
25 24 23 22 21 20 19
1 0 0 P U S W L
cond
16 15
Rn
<add mode>
IA: Increment after.
IB: Increment before.
DA: Decrement after.
DB: Decrement before.
In a non-user mode, CPSP may be restored by:
LDM|{<cond>}<add mode>
0
register list
base register
load/store
write-back (auto-index)
restore PSR and force user bit
up/down
pre-/post-index
Rn{!}, <registers, PC>^
Full or empty: The stack pointer can either point to the last item in the stack (a full
stack), or the next free space on the stack (an empty stack).
嵌入式系統架構軟體設計
---using ARM
Example Addressing Mode for LDM/STM
STMIB R9!, {R0,R1,R5}
STMIA R9!, {R0,R1,R5}
Empty
R9'
R9
0x1018
R5
0x1014
R1
0x1010
R0
0x100C
R9'
R5
0x1018
R1
0x1014
R0
0x1010
R9
0x100C
0x1008
0x1008
0x1004
0x1004
0x1000
0x1000
STMDB R9!, {R0,R1,R5}
STMDA R9!, {R0,R1,R5}
0x1018
0x1018
0x1014
0x1014
0x1010
R9
R5
0x100C
R1
0x1008
R0
R9'
0x1004
0x1000
0x1010
R9
R9'
0x100C
R5
0x1008
R1
0x1004
R0
0x1000
Full
嵌入式系統架構軟體設計
---using ARM
ISR Example
 e.g. Interrupt handler
__irq void IRQHandler(void)
{
volatile unsigned int *base=(unsigned int *) 0x80000000;
If (*base==1)
C_int_handler_1( );
IRQHandler PROC
*(base+1)=0;
STMFD spl,{r0-r4, r12, lr}
}
MOV
LDR
SUB
CMP
BLEQ
MOV
STR
ADD
LDMFD
SUBS
r4,#0x80000000
r0, [r4,#0]
sp,sp,#4
r0,#1
C_int_handler
r0,#0
r0,[r4,#4]
sp, sp, #4
spl,{r0-r4, r12, lr}
pc, lr, #4
Swap Memory and Register Instruction
Binary Encoding
嵌入式系統架構軟體設計
---using ARM
Assembly Format:
SWP{<cond>}{B} Rd,Rm,[Rn]
31
28 27
cond
16 15
23 22 21 20 19
B
0 0 010
0 0
Rn
12 11
Rd
4 3
0
Rm
0 0 0 0 1 0 0 1
destination register
base register
source register
unsigned byte/word
Rd
1
Rn
2
Rm
嵌入式系統架構軟體設計
---using ARM
SWP Example
ADR r0, SEMAPHORE
SWPB r1, r1, [r0]
; exchange byte
r1
r0
0
r?
Status Register to General Register Transfer
Instruction Binary Encoding
嵌入式系統架構軟體設計
---using ARM
Assembly Format:
MRS{<cond>}
Rd,CPSR|SPSR
31
28 27
cond
16 15
23 22 21
0 0 010
R
0 0 1 1 1 1
12 11
Rd
0 0 0 0 0 0 0 0 0 0 0 0
destination register
SPSR/CPSR
E.g.
MRS r0, CPSR
MRS r3, CPSR
; move the CPSR to r0
; move the SPSR to r3
Note:
The SPSR form should not be used in user or system mode.
0
Transfer to Status Register Instruction
Binary Encoding
嵌入式系統架構軟體設計
---using ARM
Assembly Format:
MRS{<cond>}
CPSR_f|SPSR_f, #<32-bit immediate>
MRS{<cond>}
CPSR_<field>|SPSR_<field>, Rm
31
28 27 26 25 24 23 22 21 20 19
cond
00
# 1 0 R 1 0
16 15
field
12 11
0
1 1 1 1
operand
field mask
SPSR/CPSR
25
11
1
8 7
#rot
0
8-bit immediate
immediate alignment
25
11
0
<field>
C - the control field – PSR[7:0]
X – the extension field – PSR[15:8]
S – the status field – PSR[23:16]
F – the flags field – PSR[31:24]
4 3
0 0 0 0 0 0 0 0
operand register
0
Rm
嵌入式系統架構軟體設計
---using ARM
 Set N, C,V, Z flags:
MSR CPSR_f, #&f0000000
 Set C flag, preserving N, Z, and V
MRS r0, CPSR
ORR
r0, r0, #&20000000
MSR CPSR_f, r0
MSR Example
; set all the flags
; move the CPSR to r0
; set bit 29 of r0
: move back to CRSR
嵌入式系統架構軟體設計
---using ARM
練習：切換ARM操作模式
 寫一段程式，將ARM由Supervisory mode切換到IRQ mode。
 用ADS環境。
31 30 29 28 27
N Z C V Q
24
J
undefined
7 6 5 4
0
I F T mode
 Mode bits
 Specify the processor mode
 10000
User
 10001
FIQ
 10010
IRQ
 10011
SVC
 10111
Abort
 11011 Undef
 11111 System
嵌入式系統架構軟體設計
---using ARM
 There are 3 types:
 Coprocessor data operations
Coprocessor Instructions
ARM
Co-processor
• CDP: initiate a coprocessor data processing operation
 Coprocessor Register transfers
• MRC: Move to ARM register from coprocessor register
• MCR: Move to coprocessor register from ARM register
 Coprocessor Memory transfer
• LDC: load coprocessor register from memory
• STC: store from coprocessor register to memory
嵌入式系統架構軟體設計
---using ARM
Exception-generating &
Semaphore Instructions
 SWI
 Used to cause a Software Interrupt exception to occur
SWI {<cond>} <immed_24>
SWI 0x123456
 BKPT
 Used from software breakpoints in ARM architecture 5 or above. Cause
a Prefetch Abort exception to occur.
BKPT <immediate>
嵌入式系統架構軟體設計
---using ARM
Summary of ARM Architectures
Core
Architecture
ARM1
v1
ARM2
v2
ARM2as, ARM3
v2a
ARM6, ARM600, ARM610
v3
ARM7, ARM700, ARM710
v3
ARM7TDMI, ARM710T, ARM720T, ARM740T
v4T
StrongARM, ARM8, ARM810
v4
ARM9TDMI, ARM920T, ARM940T
v4T
ARM9ES, XScale Microarchitecture
v5TE
ARM10TDMI, ARM1020E
v5TE
926EJ-S/1026EJ-S
v5TEJ
嵌入式系統架構軟體設計
---using ARM
Reference
 S. Furber, ARM system-on-chip Architecture, 2nd ed. Addison-Wesley
 Seal. ARM architecture reference manual, 2nd ed. Addison-Wesley
 ARM Development Suite User Guide
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
--- using ARM
Module #3-5: Important ARM ASM Programming Skills
嵌入式系統架構軟體設計
---using ARM
 Direct loading with MOV and MVN
 Loading with LDR Rd,=const
Load Constant into Register
嵌入式系統架構軟體設計
---using ARM
Direct Load Constant into Register
 Mov{cond}{S},Operand2
 Load immediate constant to register
 E.g.
• MOV R1,0x18 ;R1=0x18
 Can load any 8-bit constant, giving a range of 0x00 to 0xFF
 MVN: load the bitwise complement of these values. The numerical values are –(n+1).
Register
Binary
Decimal
No rotate
000000000000000000000000xxxxxxxx 0-255
Right. 30 bits 0000000000000000000000xxxxxxxx00 0-1020
Right. 28 bits 00000000000000000000xxxxxxxx0000 0-4080
Right. 26 bits 000000000000000000xxxxxxxx000000 0-16320
…
…
Right. 8 bits xxxxxxxx000000000000000000000000 0-255 x 224
Right. 6 bits
Right. 4 bits
Right. 2 bits
xxxxxx000000000000000000000000xx xxxx000000000000000000000000xxxx xx000000000000000000000000xxxxxx -
Step
1
4
16
64
…
224
-
Hexadecimal
0-0xFF
0-0x3FC
0-0xFF0
0-0x3FC0
…
0-0xFF000000
-
Compiler ERROR MSG: Immediate n out of range for this operation.
嵌入式系統架構軟體設計
---using ARM
Loading with LDR Rd,=const
 The LDR Rd,=const pseudo-instruction can construct any 32-bit numeric
constant in a single instruction
 The LDR pseudo-instruction generates the most efficient code for a specific
constant:
 If the constant can be constructed with a MOV or MVN instruction, the
assembler generates the appropriate instruction.
 If the constant cannot be constructed with a MOV or MVN instruction,
the assembler:
• Places the value in a literal pool.
• Generates an LDR instruction with a program-relative address that reads the
constant from the literal pool.
 e.g.:
LDR Rn,[pc,#offset to literal pool]
;load register n with one word from the address [pc+offset]
Literal Pool: A portion of memory embedded in the code to hold constant values.
嵌入式系統架構軟體設計
---using ARM
LDR & Literal Pool Example
; ; c:\ARM\ADSv1_2\Examples\asm\loadcon.s
AREA
Loadcon, CODE, READONLY
ENTRY
START
BL
func1
BL
func2
stop MOV r0,#0x18
; =>MOV R0, #42
LDR
r1, =0x20026
SWI
0x123456
func1
LDR
r0, =42
; =>MOV R0, #42
LDR
r1, =0x55555555
; =>LDR R1, [PC, #offset to Literal Pool l]
LDR
r2, =0xFFFFFFFF
; =>MVN R2, #0
MOV pc, lr
LTORG
Litetal Pool l constains
Litetal 0x55555555
func2
LDR
r3, =0x55555555
; =>LDR R3, [PC, #offset to Literal Pool l]
LDR
r4, =0x66666666
; If this is uncommented it is out of reach
; fails, because Literal Pool 2
MOV pc, lr
LargeTable
SPACE 4200
; Starting at the current location
; clears a 4200 bytes area of memory
; to zero, reserves a zeroed block of memory
; Literal Pool 2 is empty
END
嵌入式系統架構軟體設計
---using ARM
Loading Addresses into Registers
 Direct loading with ADR and ADRL
 Loading addresses with LDR Rd, =label.
嵌入式系統架構軟體設計
---using ARM
Direct Loading with ADR
 The assembler converts an ADR Rn, label pseudo-instruction by generating:
 A single ADD or SUB instruction that loads the address, if it is in range
 An error message if the address cannot be reached in a single instruction.
 The offset range is 255 bytes for an offset to a non word-aligned address,
and 1020 bytes (255 words) for an offset to a word-aligned address.
 E.g.
• ADR r2, Label+1000
• ADR r2, Label +211
嵌入式系統架構軟體設計
---using ARM
Direct Loading with ADRL
 The assembler converts an ADR Rn, label pseudo-instruction by generating:
 Two data-processing instruction that load the address, if it is in range
 An error message if the address cannot be constructed in two instructions
 The range of an ADRL pseudo-instruction is 64KB for a non wordaligned address and 256 KB for a word-aligned address.
 E.g.
• ADRL r2, Label +4300
嵌入式系統架構軟體設計
---using ARM
ADR and ADRL Example
; c:\ARM\ADSv1_2\Examples\asm\adrlabel.s
AREA
adrlabel, CODE, READONLY
ENTRY
START
BL
func
stop
MOV r0,#0x18
; angel_SWIreason_ReportException
LDR
r1,=0x20026
; ADP_Stopped_ApplicationExit
SWI
0x123456
; ARM semihosting SWI
LTORG
; Create a literal pool
Func
ADR
r0, Start
; =>SUB r0, PC, #offset to Start
ADR
r1, DataArea
; =>ADD r1, PC, #offset to DataArea
;ADR r2, DataArea+4300
; =>This would fail because the offset
; cannot be expressed by operand2 of an ADD
ADRL r2, DataArea+4300
; =>ADD r2, r2, #offset1
; ADD r2, r2, #offset2
MOV pc, lr
; Return
DataArea
SPACE 8000
END
; Starting at the current location.
; clears a 8000 byte area of memory to zero
嵌入式系統架構軟體設計
---using ARM
Loading Addresses with LDR Rd,=label
 Load any 32-bit constant into a register
 The assembler converts an LDR r0,=label pseudo-instruction by:
 Placing the address of label in a literal pool (a portion of memory
embedded in the code to hold constant values).
 Generating a program-relative LDR instruction that reads the address
from the literal pool, for example:
LDR rn [pc, #offset to literal pool ]
; load register n with one word from the address [ pc + offset ]
嵌入式系統架構軟體設計
---using ARM
Example for LDR Rd, =label
; c:\ARM\ADSv1_2\examples\asm\ldriabel.s
AREA
LDRlabel, CODE, READONLY
ENTRY
START
BL
func1
BL
func2
stop
MOV r0,#0x18
LDR r1,=0x20026
SWI 0x123456
func1
LDR r0, =start
; =>LDR R0, [PC, #offset into Literal Pool 1]
LDR r1, =Darea+12
; =>LDR R1, [PC, #offset into Literal Pool 1]
LDR r2, =Darea+6000
; =>LDR R2, [PC, #offset into Literal Pool 1]
MOV pc, lr
LTORG
; Litetal Pool l
func2
LDR r3, =Darea+6000
; =>LDR R3, [PC, #offset into Literal Pool 1](sharing with previous literal)
;LDR r4, =Darea+6004
; If uncommented produces an error as Literal Pool 2 is out of range
MOV pc, lr
Darea
SPACE 8000
; Literal Pool 2 is out of range of the LDR instructions above
END
嵌入式系統架構軟體設計
---using ARM
; c:\ARM\ADSv1_2\examples\asm\jump.s
AREA
Jump, CODE, READONLY
CODE32
Num EQU
2
ENTRY
START
MOV
r0,#0
MOV r0,#3
MOV r0,#2
BL
arithfunc
stop MOV r0,#0x18
LDR
r1,=0x20026
SWI
0x123456
arithfunc
CMP
r0, #num
MOVHS pc, lr
ADR
r3, JumpTable
LDR
pc, [R3,R0,LSL#2]
LTORG
JumpTable
DCD
DoAdd
DCD
DoSub
DoAdd
ADD
r0, r1, r2
MOV pc, lr
DoSub
SUB
r0, r1, r2
MOV pc, lr
END
Exercise: Implement a Jump Table
; Number of entries in jump table
; Set up the three parameters
; Call the function
; Label the function
; Treat function code as unsigned integer
; if code is >=num then simply return
; load address of jump table
; Jump to the appropriate routine
; Operation 0
; Return
; Operation 1
; Return
; Mark the end of the file
Trace this program!
And make a flow chart.
嵌入式系統架構軟體設計
---using ARM
; c:\ARM\ADSv1_2\examples\asm\strcopy.s
AREA
StrCopy, CODE, READONLY
ENTRY
Start
LDR
r0,=srcstr
LDR
r0,=dststr
BL
strcopy
Stop
MOV
r0,#0x18
LDR
r1,=0x20026
SWI
0x123456
strcopy
LDRB
r2, [r1],#1
STRB
r2, [r0],#1
CMP
r2, #0
BNE
strcopy
MOV
pc, lr
AREA
srcstr
dststr
END
Exercise: String Copy
Trace this program!
And make a flow chart.
; Point to first string
; Point to second string
; Call subroutine to do copy
; Load byte and update address
; Store byte and update address
; Check for zero terminator
; Keep going if not
Strings, DATA, READWRITE
DCB
"First string-source",0
DCB
"Second string-destination",0
嵌入式系統架構軟體設計
---using ARM
Load and Store Multiple Register Instructions
 An efficient way of moving the contents of several registers to and from
memory
 Used for block copy and for stack operations at subroutine entry and exit
 The advantages include: (Compare to single L/S)
 Smaller code size
 Single instructions fetch overhead
 On uncached ARM processors, the first word of data transferred by a
load or store multiple is always a nonsequential memory cycle, but
all subsequent words transferred can be sequential memory cycles.
嵌入式系統架構軟體設計
---using ARM
LDM and STM Instructions
 The load ( or store ) multiple instruction loads (stores) any subset of the 16
general-purposes registers from (to) memory, using a single instruction.
 Syntax:
 LDM {cond} address-mode Rn{1}, reg-list{^}
 !:Specifies base register write back. If this is specified, the address in the
base register is updated after the transfer.
 ^:Specifies that the CPSR is restored from the SPSR. It must be used
only from a privileged mode (i.e. other than user mode).
 E.g.
 LDMIA
 STMIA
r0!, {r2-r9}
r1, {r0-r10}.
嵌入式系統架構軟體設計
---using ARM




Addressing Mode for LDM/STM
IA: Increment after
IB: Increment before
DA: Decrement after
DB: Decrement before
 Full of empty: The stack pointer can either point to the last item in the stack
(a full stack), or the next free space on the stack (an empty stack).
 Note: The ARM-Thumb Procedure Call Standard (ATPCS), and ARM and
Thumb C and C++ compiles always use a full descending stack.
嵌入式系統架構軟體設計
---using ARM
Example Addressing mode for LDM/STM
STMIB R9!, {R0,R1,R5}
STMIA R9!, {R0,R1,R5}
Empty R9'
R9
0x1018
R5
0x1014
R1
0x1010
R0
0x100C
R9'
R5
0x1018
R1
0x1014
R0
0x1010
R9
0x100C
0x1008
0x1008
0x1004
0x1004
0x1000
0x1000
STMDB R9!, {R0,R1,R5}
STMDA R9!, {R0,R1,R5}
0x1018
0x1018
0x1014
0x1014
0x1010
R9
R5
0x100C
R1
0x1008
R0
R9'
0x1004
0x1000
0x1010
R9
R9'
0x100C
R5
0x1008
R1
0x1004
R0
0x1000
Full
嵌入式系統架構軟體設計
---using ARM
Stacking Registers for Nested Subroutines
Subroutine STMFD sp!, {r5-r7,r}
……
; code
….
BL
; Push work registers and lr
Note: Your codes use r5,r6,r7,lr
xxxx_xxxx
……
; code
……
LDMFD
sp!, {f5-f7,pc}
; Pop work registers and pc
嵌入式系統架構軟體設計
---using ARM
$Label
$Label
Using Macro
MACRO
TestAndBranch $dest,$reg,$cc
CMP
$reg, #0
B$cc
$dest
MEND
This macro can be invoked as follows:
test TestAndBranch Non Zero, r0, NE
…
…
NonZero
After substitution this becomes:
test
CMP r0, #0
BNE NonZero
…
…
NonZero
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #4-1: ARM-Thumb Interworking
嵌入式系統架構軟體設計
---using ARM
Outline
C
ARM
C++
Thum b
ARM-Thumb Procedure Call
Standard (ATPCS)
嵌入式系統架構軟體設計
---using ARM
 To ensure that separately
compiled or assembled
subroutines can work together.
 Register roles and names
 The stack
 A full, descending stack
 Eight-byte alignment at
all external interfaces.
Register roles and names in ATPCS
Register
r15
r14
r13
r12
r11
r10
Synonym
v8
v7
Special
pc
lr
sp
ip
r9
v6
sb
r8
r7
v5
v4
wr
r6
r5
r4
r3
r2
r1
r0
v3
v2
v1
a4
a3
a2
a1
-
sl
Role in the procedure call standard
Program counter.
Link register.
Stack pointer.
Intra-procedure-call scratch register.
ARM-state variable register 8.
ARM-state variable register 7. Stack limit
pointer in stack-checked variants.
ARM-state variable register 6. Static base
in RWPI variants.
ARM-state variable register 5.
Variable register 4. Thumb-state work
register.
Variable register 3.
Variable register 2.
Variable register 1.
Argument/result/scratch register 4.
Argument/result/scratch register 3.
Argument/result/scratch register 2.
Argument/result/scratch register 1.
嵌入式系統架構軟體設計
---using ARM
Parameter Passing
 Nonvariadic: A routine with a fixed number of arguments is.
 The first integer arguments are allocated to r0-r3 in order.
 Remaining parameters are allocated to the stack in order.
 Variadic routine: A routine with a variable number of arguments.
 a1-a4, a1 first.
 The stack, lowest address first.
#include <stdarg.h>
int ShowVar(char *szTypes, ...)
{
va_list vl;
va_start (vl, szTypes);
...
}
void main()
{
ShowVar("fcsi",32,4f,'a',"Test string",4);
}
嵌入式系統架構軟體設計
---using ARM
When to Use Interworking
 Code density
 Thumb state has better code density
 Speed consideration
 Running in ARM state has better efficiency than Thumb state.
 Functionality
 Thumb instructions are less flexible than their ARM equivalents.
 Some operations are not possible in thumb state.
• e.g. enable/disable interrupt & A state change.
 Exception handing
 The processor automatically enters ARM state when a processor exception
occurs.
 This means that the first part of an exception handler must be coded with ARM
instructions, even if it re-enters Thumb state to carry out the main processing of
the exception.
 Standalone Thumb programs
 A thumb-capable ARM processor always starts in ARM state.
嵌入式系統架構軟體設計
---using ARM
Non-interworking Function Call
 Implementing a function call usually requires two steps:
 Store the return address in the link register (LR)
 Branch to the address of the required function
void mouse()
{
…
monkey();
…
}
; mouse()
…
BL monkey
…
void monkey()
{
…
return();
}
; monkey()
…
MOV pc, lr
嵌入式系統架構軟體設計
---using ARM
ARM/Thumb Interworking Function Call
 Use BX or BLX
 BX does not store return address in LR automatically.
 -> return from function by BX LR to original state.
 v5T supports BLX
(1)
B{L} X {<cond>} Rm
31
28 27
cond
(2)
31
6
0 001001011111111111100
5 4 3
Rm
L 1
0
BLX <Target address>
28 27
1111
10
25 24 23
1 H
0
24-bit signed word offset
嵌入式系統架構軟體設計
---using ARM
BLX Example
 A call to Thumb subroutine:
TSUB
CODE32
…..
BLX
TSUB
….
CODE16
….
BX
r14
; ARM code follows
; call thumb routine
; start of Thumb code
; Thumb subroutine
; return
嵌入式系統架構軟體設計
---using ARM
AREA
ENTRY
ARM/Thumb Interworking Example
AddReg. CODE,READONLY
;Name this block of code.
; Mark first instruction to call.
main
ADR r0, ThumbProg + 1
BXr0
CPSR
nzcvqIFT_SVC
;Generate branch target address
; and set bit 0, hence arrive
; at target in Thumb state.
; Branch exchange to ThumbProg
CODE16
; Subsequent instructions are Thumb code
MOV r2,#2
MOV r3,#3
ADD r2,r2,r3
ADR r0,ARMProg
BX r0
CPSR
; Load r2 with value 2
; Load r2 with value 3
; r2=r2+r3
ThumbProg
nzcvqIFT_SVC
CODE32
; Subsequent instructions are ARM code.
ARMProg
MOV r4,#4
MOV r5,#5
ADD r4,r4,r5
CPSR
Stop
MOV r0,#0x18
LDR r1, =0x20026
SWI 0x123456
END
nzcvqIFt_SVC
; angel_SWIreason_ReportException
; ADP_Stopped_ApplicationExit
;ARM semihosting SWI
; Mark end of this file
嵌入式系統架構軟體設計
---using ARM
練習：ARM/Thumb Interworking #1
 Trace code:
 \ADSv1_2\example\asm\thumbsub.mcp
 Monitor CPSR with PC
嵌入式系統架構軟體設計
---using ARM
C Functions&Interworking
 Compiler C to run in Thumb&support interworking
 tcc -c-g-O1-apcs/interwork thumbmain.c
 Compiler C to run in ARM state & support intherworking
 armcc -c-g-O1 -apcs/interwork armsub.c
 Link
 armlink thumbmain.o armsub.o -o thumbtoarm.axf -info veneers
Void xxx()
{
…
func();
…
}
; By armcc –apcs/interwork
xxx
STMFD SP!, {r4-r11, lr}
…
BL sub
…
LDMFD SP!, {r4-r11, lr}
BX lr
;By tcc –apcs/interwork
xxx
PUSH SP!, {r4-r7,lr}
…
BL sub
…
POP SP!, {r4-r7, lr}
POP {r3}
BX
r3
嵌入式系統架構軟體設計
---using ARM
練習：ARM/Thumb Interworking #2
\ADSv1_2\examples\interwork\*.c
1. ARM (main) code calling a Thumb subroutine
armcc -c-g-O1 - apcs/interwork armmain.c
tcc -c -g-O1 -apcs/interwork thumbsub.c
armlink armmain.o thumbsub.o -o armtothumb.axf -info veneers
2. Thumb (main) code calling an Arm subroutine
tcc -c-g-O1 -apcs/interwork thumbmain.c
armcc -c -g-O1 –apcs/interwork armsub.c
armlink thumbmain.o armsub.o -o thumbtoarm.axf -info veneers
 Run the code by AXD
嵌入式系統架構軟體設計
---using ARM
 Inline Assembler
 C calls ASM function
 ASM call C function
Mixing C & Assembler
嵌入式系統架構軟體設計
---using ARM
Inline Assembler
 The ARM C compiler support inline assembly language with the
___asm specifier.
 The ARM C++ compilers support the asm syntax proposed in the
ANSI C++ Standard, with the restriction that the string literal must
be a single string. e.g:
 asm(“instruction[;instruction]”);
 ARM C++ supports the C compiler ___asm sytax.
___asm
{
instruction [; instruction]
…
[instruction]
}
嵌入式系統架構軟體設計
---using ARM
Restriction of Inline Assembler
 Not support
 LDR Rn, =express
 Label expression
 ADR, ADRL
 & can’t be used to express hex. (use 0x prefix instead)
 BX, BLX
 Can’t write to PC
嵌入式系統架構軟體設計
---using ARM
#include <stdio.h>
int main(void)
{
const char *a=“Hello world!”;
char b[20];
__asm
{
MOV
R0, a
MOV
R1, b
BL
my_strcpy, {R0, R1}
}
printf(“Original string: %s\n”,a);
printf(“Copied string: %s\n”,b);
return 0;
}
String Copy Example
Void my_strcpy(char *src, const char *dst )
{
int ch;
___asm
{
loop:
#ifndef___thumb
// Arm version
LDRB
ch,[src], #1
STRB
ch,[dst],#1
#else
//Thumb version
LDRB
ch, [src]
ADD
src,#1
STRB
ch,[dst]
ADD
dst,#1
#endif
CMP
ch,#0
BNE
loop
}
}
嵌入式系統架構軟體設計
---using ARM
Some Issues to Use Inline Assembler
 Use r0-r3, ip, lr and CPSR with caution.
 E.g.
Int funct(int x)
{
….
__asm
{
add r0,r0,#1
}
add x,x,#1
//we can’t assert x is in r0
//correct usage
 Don’t save &restore physical registers.
 E.g.
int funct(int x)
{
….
__asm
{
stmfd
add
eor
ldmfd
}
}
sp! {r0}
r0,x,1
x,r0,x
sp!, {r0}
//save r0
//restore r0
嵌入式系統架構軟體設計
---using ARM
; int f(int i) {return g(i,2*i,3*i,4*i,5*i);}
ASM calls C example
int g(int a, int b, int d, int e)
{
return a+b+c+d+e;
}
EXPORT f
AREA f, CODE, READONLY
IMPORT g
; i is in r0
str LR,[SP, #-4]!
; preserve lr
ADD r1,r0,r0
; computer 2*i (2nd param)
ADD r2,r1,r0
; computer 3*i (3nd param)
ADD r3,r1,r2
; computer 5*i
STR r3, [sp,#4]!
; 5th param on stack
ADD r3,r1,r1
; computer 4*i (4nd param)
BL g
; branch to C function
ADD sp, sp, #4
; remove 5th param
LDR pc,[sp],#4
; return
END
嵌入式系統架構軟體設計
---using ARM
Access C Global Variables
 Use “IMPORT”
 Use “LDR/STR”
 E.g.
AREA
global_variable, CODE, READONLY
EXPORT asmsub
IMPORT glob_var
asmsub
ldr
ldr
add
str
mov
END
r1,=glob_var
r0, [r1]
r0, r0, #10
r0, [r1]
pc, lr
; read address of glob_var
; into r1 from literal pool
嵌入式系統架構軟體設計
---using ARM
C call ASM Example
install_directory\example\asm as strtest.c and scopy.s
#include <stdio.h>
extern void strcopy(char*d, const char *s);
int main()
{ const char *srcstr = “First string -source”;
char dststr[] = “Second string - destination”;
/ *dststr is an array since we’re going to change it*/
printf(“Before copying:\n”);
printf(“%s\n %s\n”,srcstr,dststr);
strcopy(dststr,srcstr);
printf(“After copying:\n”);
printf(“ %s\n %s\n”,srcstr,dststr);
return(0);
}
AREA SCopy,CODE,REAONLY
EXPORT strcopy
strcopy ; r0 points to destination string.
; r1 points to source string.
LDRB r2,[r1],#1
; Load byte and update address.
STRB r2,[r0],#1
; Store byte and update address.
CMP r2,#0
; Check for zero terminator.
BNE strcopy
; Keep going if not.
MOV pc,lr
; Return.
END
嵌入式系統架構軟體設計
---using ARM
練習：Inlie IRQ Controller
 分別寫一個disable interrupt 和enable interrupt 的inline
assembler subroutine。
__inline void enable_IRQ(void)
{
…..
}
__inline void disable_IRQ(void)
{
…..
}
 在c 的main function 去呼叫執行
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #4-2: ARM Exception Handler
嵌入式系統架構軟體設計
---using ARM
Exception Type & Vector Address
...
SW I handler
IRQ handler
Exception type
Mode
Reset
Supervisor
Undefined instructions
Undefined
Software interrupt (SWI)
Supervisor
Prefetch Abort (instruction fetch memory abort)
Abort
Data Abort (data access menory abort)
Abort
IRQ (interrupt)
IRQ
FIQ (fast interrupt)
FIQ
Normal address High vector address
0x00000000
0xFFFF0000
0x00000004
0xFFFF0004
0x00000008
0xFFFF0008
0x0000000C
0xFFFF000C
0x00000010
0xFFFF0010
0x00000018
0xFFFF0018
0x0000001C
0xFFFF001C
Literal pool
FIQ
IRQ
0x1C
0x18
(Reserved)
0x14
Data Abort
0x10
0x0C
0x08
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
Vector table
0x04
0x00
嵌入式系統架構軟體設計
---using ARM
Exception Handling by ARM Core
 When an exception occurs, the banked versions of R14 and the SPSR for
the exception mode are used to save state as follows:
1. R14_<exception_mode> = return link
2. SPSR_<exception_mode> = CPSR
3. CPSR[4:0] = exception mode number
4. CPSR[5] = 0
/*Execute in ARM state*/
5. if <exception_mode> = = Reset or FIQ then??
6. CPSR[6] = 1
/*Disable fast interrupt else CPSR[6] is unchanged*/
7. CPSR[7] = 1
/* Disable normal interrupts*/
Priority
Exception
8. PC = exception vector address
Highest 1
 Summary:
 Copy PC into r14_mode, save CPSR into SPSR
 Change to appropriate exception mode
 PC is force to 0x0-0x1c
Lowest
Reset
2
Data Abort
3
FIQ
4
IRQ
5
Prefetch Abort
6
Undefined
instruction
SWI
嵌入式系統架構軟體設計
---using ARM
Reset Exception
1. R14_svc = UNPREDICTABLE value
2. SPSR_svc = UNPREDICTABLE value
3. CPSR[4:0] = 0b10011
/*enter supervisory mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6] = 1
/*Disable fast interrupts*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF0000
else
PC = 0x00000000
嵌入式系統架構軟體設計
---using ARM
Undefined Instruction Exception
 While to execute an co-processor instruction, ARM can’t get response from
co-processor.
 Attempt to execute an instruction that is UNDEFINED.
 Can be used for software emulation of a coprocessor in a system that does
not have physical coprocessor.
 Action performed:
1. R14_und = address of next instruction after the undefined instruction
2. SPSR_und = CPSR
3. CPSR[4:0] = 0b11011
/*enter Undefined mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6]
/*unchanged*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF0004
else
PC = 0x00000004
嵌入式系統架構軟體設計
---using ARM
Software Interrupt
 Software Interrupt Instruction (SWI) enters supervisor mode.
 Action performed:
1. R14_svc = address of next instruction after the undefined instruction
2. SPSR_svc = CPSR
3. CPSR[4:0] = 0b10011
/*enter supervisor mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6]
/*unchanged*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF0008
else
PC = 0x00000008
Return from Undefined Instruction
&Software Interrupt Exceptions
嵌入式系統架構軟體設計
---using ARM
 Simple
MOVS
 In exception handler
STMFD
….
LDMFD
pc, lr
sp!, {reglist, lr}
sp!, {reglist, pc}^
^: Auto restore CPSR from SPSR.
嵌入式系統架構軟體設計
---using ARM
Prefetch Abort Exception
 If processor attempts to fetch an instruction from an illegal address, the
instruction is marked as invalid. (in pipeline)
 When reach the invalid instruction, prefetch abort exception is generated.
1. R14_abt = address of aborted instruction +4
2. SPSR_abt = CPSR
3. CPSR[4:0] = 0b10111
/*enter Abort mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6]
/*unchanged*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF000C
else
PC = 0x0000000C
嵌入式系統架構軟體設計
---using ARM
 Simple
SUBS
 Exception handler
SUBS
STMFD
…..
LDMFD
Return from Prefetch Abort Exception
pc, lr,#4
lr,lr,#4
sp!, {reglist, lr}
sp!, {reglist, pc}^
嵌入式系統架構軟體設計
---using ARM
 Signaled by the memory system.
 Action performed:
1. R14_abt = address of aborted instruction +8
2. SPSR_abt = CPSR
3. CPSR[4:0] = 0b10111
/*enter Abort mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6]
/*unchanged*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF0010
else
PC = 0x00000010
Data Abort
嵌入式系統架構軟體設計
---using ARM
 Simple
SUBS
 Exception handler
SUBS
STMFD
….
LDMFD
Return from Data Abort Exception
pc, lr,#8
lr,lr,#8
sp!, {reglist, lr}
sp!, {reglist, pc}^
嵌入式系統架構軟體設計
---using ARM
FIQ Exception Handling by ARM
When an FIQ is detected, the following actions are performed:
R14_fiq = address of next instruction to be executed +4
SPSR_fiq = CPSR
CPSR[4:0] = 0b10001
/*enter FIQ mode*/
CPSR[5] = 0
/*Execute in ARM state*/
CPSR[6] = 1
/*Disable fast interrupts*/
CPSR[7] = 1
/*Disable normal interrupts*/
If high vectors configured then
PC = 0xFFFF001C
else
Update PC
PC = 0x0000001C
Store PC+4 to R14
To return after servicing the interrupt, use:
SUBS PC, R14,#4
Xx+0
Xx+4
Xx+8
嵌入式系統架構軟體設計
---using ARM
FIQ Exception Handler by Programmer
 Your FIQ handler
SUBS
STMFD
….
….
LDMFD
lr, lr,#4
sp!, {r0-r4, lr}
sp!, {r0-r4, pc}^
Xx+0
Update PC
Xx+4
Store PC+4 to R14
Xx+8
嵌入式系統架構軟體設計
---using ARM
IRQ Exception
 Action performed:
1. R14_irq = address of next instruction to be executed +4
2. SPSR_abt = CPSR
3. CPSR[4:0] = 0b10010
/*enter IRQ mode*/
4. CPSR[5] = 0
/*Execute in ARM state*/
5. CPSR[6]
/*unchanged*/
6. CPSR[7] = 1
/*Disable normal interrupts*/
7. If high vectors configured then
PC = 0xFFFF0018
else
PC = 0x00000018
 Return
 SUBS
pc,lr,#4
嵌入式系統架構軟體設計
---using ARM
Implement a SWI Handler
 \ADSv1_2\examples\swi\*
main.c
installs the SWI vector in the exception table, then calls SWIs (0, 1, 2 & 3)
via__swi().
ahandle.s
top-level SWI handler written in assembler. Identify ARM&thumb SWIs
then pass to chandle.c for processing.
chandle.c
second-level SWI handler, called from ahandle.s.
SWIs 0, 1, 2 & 3 execute some simple arithmetic.
Swi.h
contains the definitions of __swi(), __swi(1), __swi(2) &__swi(3).
嵌入式系統架構軟體設計
---using ARM
Calling SWI from An Application
 In assembly, set up required register values then issue SWI.
MOV
r0,#65
SWI 0x0
;call SWI 0x0 with parameter value in r0
 C/C++, declare the SWI as an __SWI function, and call it.
 ___swi() void my__swi(int);
…
 my__swi(65);
 Provide that:
 Any arguments are passed in r0-r3 only.
 Any results are returned in r0-r3 only.
• If there are 2-4 return values, those must be returned by a structure.
Directive as __value_in_regs
嵌入式系統架構軟體設計
---using ARM
SWI Function Declare&Usage
// from example\SWI\swi.h
__swi(0) int multiply_two(int, int);
__swi(1) int add_two(int, int);
__swi(2) int add_multiply_two(int, int, int, int);
struct four_results
{
int a;
int b;
int c;
int d;
};
__swi(3) __value_in_regs struct four _results many_operations(int, int, int, int);
// calling example
structure four_results res_3;
res_3 = many_operations(1, 2, 3, 4);
add_two(1, 2);
嵌入式系統架構軟體設計
---using ARM
Parameters Passing
 We can pass values in and out of a SWI handler written in C, provided that
the top-level handler passes the stack pointer into the C function as the
second parameter.
MOV
r1, sp
BL C_SWI_Handler




Parameter0 = reg[0]
Parameter1 = reg[1]
Parameter2 = reg[2]
Parameter3 = reg[3]
lr_SVC
r3
Re g[3]
r2
 Write back
 reg[0] = updated_value_0
 reg[1] = updated_value_1
 reg[2] = updated_value_2
 reg[3] = updated_value_3
r1
r0
Sp_SVC
Re g[0]
嵌入式系統架構軟體設計
---using ARM
Identify SWI
 When a SWI handler is entered, it must establish which SWI is being called.
 Load the SWI instruction that cause the exception.
• LDR
r0, [lr, #-4]
 Extract the SWI number by clearing the 31-24 bits.
• BIC
31
r0,r0,#0xFF000000
28 27
24 23
1 1 1 1
cond
0
24-bit (interpreted) immediate
AREA SWI_Handler, CODE, REAONLY
EXPORT SWIH
SWIH
STMFD
LDR
BIC
....
LDMFD
END
sp!, {r0-r12, lr}
r0, [lr, #-4]
r0,r0,#0xff000000
sp!, {r0-r12, pc}^
嵌入式系統架構軟體設計
---using ARM
Using SWI in Supervisory Mode
 Call a SWI in supervisory mode LR_SVC and SPSR_SVC are corrupted.
 Therefore, we must store LR_SVC and SPSR_SVC when a SWI is called.
MRS
STMFD
….
LDMFD
MSR
r0, spsr
sp!, {r0}
; Get spsr
; Store spsr onto stack
sp!, {r0}
spsr_cf, r0
; get spsr from stack
; restore spsr
嵌入式系統架構軟體設計
---using ARM
Identify SWI from Arm/Thumb
…..
T_bit EQU 0x20
SWI_Handler
STMFD
MOV
MRS
STMFD
TST
LDRNE
BICNE
LDREQ
BICEQ
sp!, {r0-r3, r12, lr}
r1, sp
r1, spsr
sp!, {r0}
r0, #T_bit
H r0, [lr,#-2]
r0,r0,#0xFF00
r0, [lr,#-4]
r0,r0,#0xFF000000
; Store registers
; Set pointer to parameters
; Get spsr
; Store spsr onto stack
; Occurred in Thumb state?
; Yes: Load halfword and…
; …extract comment field
; No: Load word and…
; …extract comment field
; r0 now contains SWI number
; r1 now contains pointer to stacked registers
BL
….
C_SWI_Handler
; Call main part of handler
嵌入式系統架構軟體設計
---using ARM
void C_SWI_Handler(unsigned swi_num)
{
switch(swi_num)
{
case
0:
….
break;
case
1:
….
break;
case
2:
….
break;
….
}
}
Simple C SWI Handler
嵌入式系統架構軟體設計
---using ARM
Install an Exception Handler During
Development Work
Unsigned Install_Handler(unsigned routine, unsigned *vector)
{
unsigned vec, old_vec;
vec = (routine – (unsigned)vector - 8)>>2;
//-8 for prefetching, >> for word offset
if (vec & 0xff000000)
//check is branch offset is out of limit?
{
printf(“Handler greater than 32MBytes from vector”);
}
vec = 0xea000000 | vec;
// 0xea000000 the opcode of branch inst.
old_vec = *vector;
*vector = vec;
return (old_vec);
}
Usage:
unsigned *swi_vec = (unsigned *)0x08;
extern void SWI_Handler(void);
Install_Handler((unsigned) SWI_Handler, swi_vec);
嵌入式系統架構軟體設計
---using ARM
練習：增加一個SWI功能
 利用ADS和AXD Trace \example\SWI \的範例程式
 自行增加一個運算功能swi(4) return (regs[0]+regs[1])*10。
嵌入式系統架構軟體設計
---using ARM
C Interrupt Handlers
__irq void IRQHandler (void)
{
volatile unsigned int *base = (unsigned int *) 0x80000000;
if(*base = = 1)
{
c_int_handler();
}
*(base+1) = 0;
}
Note: __irq does not provide reentrant processing
嵌入式系統架構軟體設計
---using ARM
; with__irq
IRQHandler PROC
STMFD
sp!,{r0-r4,r12,lr}
MOV
r4,#0x80000000
LDR
r0,[r4,#0]
SUB
sp,sp,#4
CMP
r0,#1
BLEQ
C_int_handler
MOV
r0,#0
STR
r0,[r4,#4]
ADD
sp,sp,#4
LDMFD
sp!,{r0-r4,r12,lr}
SUBS
pc,lr,#4
ENDP
Compiled __irq
; with__irq
IRQHandler PROC
STMFD sp!,{r4,lr}
MOV r4,#0x80000000
LDR
r0,[r4,#0]
CMP r0,#1
BLEQ C_int_handler
MOV r0,#0
STR
r0,[r4,#4]
LDMFD sp!,{r4,pc}
ENDP
嵌入式系統架構軟體設計
---using ARM
Reentrant Interrupt Handlers
 The steps needed to safely re-enable interrupts in an IRQ handler are:
1. Construct return address and save on the IRQ stack.
2. Save the work registers and spsr__IRQ.
3. Clear the source of the interrupt.
4. Switch to System mode and re-enable interrupts.
5. Save User mode link register and non callee-saved registers.
6. Call the C interrupt handler function.
7. When the C interrupt handler returns, restore User mode registers and
disable interrupts.
8. Switch to IRQ mode, disabling interrupts.
9. Restore work registers and spsr__IRQ.
10. Return from the IRQ.
嵌入式系統架構軟體設計
---using ARM
Reentrant Example
AREA INTERRUPT, CODE, READONLY
IMPORT C_irq_handler
IRQ
SUB
STMFD
MRS
STMFD
lr,lr,#4
sp!,{lr}
r14,SPSR
sp!, {r12,r14}
; construct the return address
; and push the adjusted lr_IRQ
; copy spsr_IRQ to r14
; save work regs and spsr_IRQ
; Add instruction to clear the interrupt here
; then re-enable interrupts.
MSR
CPSR_c,#0x1F
STMFD
BL
LDMFD
MSR
sp!, {r0-r3, lr}
C_irq_handler
sp!,{r0-r3, lr}
CPSR_c,#0x92
LDMFD
MSR
LDMFD
END
sp!, {r12,r14}
SPSR_cf,r14
sp!,{pc}^
; switch to SYS mode, FIQ and IRQ enabled.
; USR mode registers are now current.
; save lr_USR and non-callee saved registers
; branch to C IRQ handler.
; restore registers
; switch to IRQ mode and disable IRQs. FIQ is still enabled.
; restore work regs and spsr_IRQ
; return from IRQ.
嵌入式系統架構軟體設計
---using ARM
嵌入式系統架構軟體設計
---using ARM
Module #4-3: Build ARM ROM Image
嵌入式系統架構軟體設計
---using ARM
System Startup
Load code from address 0x0 to execute
• SVC mode
• Interrupts disable
• ARM state
Pow e r On
Boot Loade r
System initialization
N
Boot Sys te m ?
1. Initialing the execution environment,
i. e. exception vectors, stacks,
memory system, I/O, etc.
2. Initializing the C library and
application (C variables for
example).
Y
Load Sys te m
RUN
System
Exception
嵌入式系統架構軟體設計
---using ARM
System Memory Mapping
 ROM at 0x0]
 Simple
 Slow to handle exceptions
 RAM at 0x0
 Complex
 Fast to handle exceptions
RESET
0x2000000
0x0C00000
0x0020000
0x0000000
Normal/Remapped
0x2000000
0x0C00000
0x0020000
0x0000000
ROM
ROM
DRAM
DRAM
ROM
SARM
SRAM
DRAM
ROM
嵌入式系統架構軟體設計
---using ARM
General Process for Remap
1. Power on to fetch the RESET vector at 0x0
(from the aliased copy of ROM).
RESET
0x2000000
2. Execute the RESET vector:
LDR PC, =0x0C000004
This causes a jump to the real address of the
next ROM instruction
0x0C00000
0x0020000
ROM
DRAM
ROM
0x0000000
Normal/Remapped
3. Write to the REMAP register and set
REMAP = 1.
ROM
DRAM
SRAM
4. Complete the rest of the initialization code
as described in Initializing the system.
嵌入式系統架構軟體設計
---using ARM
 Reset vector is at 0x0
 Initialization process = Reset handler, to
 Set up exception vectors
 Initialize the memory system
 Initialize the stack pointer registers
 Initialize any critical I/O devices
 Change processor mode if necessary
 Change processor state if necessary
Initialize System
嵌入式系統架構軟體設計
---using ARM
Set up Exception Vectors
 If ROM at address 0x0
 Vectors consist of a sequence of hard-coded instructions to branch to
the handlers.
 If ROM at elsewhere
 Dynamically initialize the vectors by initialization codes.
 Typically, copy the vector table from ROM to RAM
嵌入式系統架構軟體設計
---using ARM
Example to Set up Exception Vectors
ENTRY
0x0
0x4
0x8
0xc
0x10
0x14
0x18
0x1c
LDR
LDR
LDR
LDR
LDR
NOP
LDR
LDR
PC, Reset_Addr
PC, Undefined_Addr
PC, SWI_Addr
PC, Prefetch_Addr
PC, Abort_Addr
; Reserved vector
PC, IRQ_Addr
PC, FIQ_Addr
IMPORT Reset_Handler
IMPORT IRQ_Handler
Reset_Addr
Undefined_Addr
SWI_Addr
Prefetch_Addr
Abort_Addr
IRQ_Addr
FIQ_Addr
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
; In init.s
; In init.s
Reset_Handler
Undefined_Handler
SWI_Handler
Prefetch_Handler
Abort_Handler
0; Reserved vector
IRQ_Handler
FIQ_Handler
; *****************
; Exception Handlers
; *****************
Undefined_Handler
B
Undefined_Handler
SWI_Handler
B
SWI_Handler
Prefetch_Handler
B
Prefetch_Handler
Abort_handler
B
Abort_handler
; IRQ_Handler
;
B
IRQ_Handler
FIQ_Handler
B
END
FIQ_Handler
嵌入式系統架構軟體設計
---using ARM
Initialize The Stack Pointer Registers
 Sp_SVC
 Must always be initialized.
 Sp_ IRQ
 Initialize it if IRQ interrupt used.
 Initialize before interrupts are enabled.
 Sp_FIQ
 Initialize it if FIQ interrupt used.
 Initialize before interrupts are enabled.
 Sp_ABT
 Initialize for Data and Prefetch Abort handling
 Sp_UND
 Initialize for Undefined Instruction handling.
 Initialize sp_ABT and sp_UND for debugging purposes.
 Set up the stack pointer sp_USR when changing to User mode to start
executing the application.
嵌入式系統架構軟體設計
---using ARM
Mode_USR
Mode_ FIQ
Mode_IRQ
Mode_SVC
Mode_ABT
Mode_UNDEF
Mode_SYS
EQU
EQU
EQU
EQU
EQU
EQU
EQU
MSR
31 30 29 18 27
24
N Z C V
J
Q
Change Processor Mode & State
0x10
0x11
0x12
0x13
0x17
0x1B
0x1F;
CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
7 6 5 4
undefined
I F
T
0
mode
 Mode bits
Specify the processor mode
 1,0000
User
 1,0001
FIQ
 1,0010
IRQ
 1,0011
SVC
 1,0111
Abort
 1,1011
Undef
1,1111
System
Example to Initialize The Stack Pointer
Registers
嵌入式系統架構軟體設計
---using ARM
Mode_IRQ
I_Bit
F_Bit
…
…
RAM_Limit
EQU
EUU
EQU
0x12
0x80
0x40
EQU
0x1000000
SVC_Stack
IRQ_Stack
.
….
…..
.
EQU
EQU
RAM_Limit
RAM_Limit-1024
;For 16MByte SDRAM
; ---Initialize stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
LDR SP, =IRQ_Stack
嵌入式系統架構軟體設計
---using ARM
Scatter Loading
 Enable us to specify the memory map of an image to armlink.
 For more information Refer to:
 ARM Developer Suite Version 1.2 Linker and Utilities Guide
嵌入式系統架構軟體設計
---using ARM
ROM_LOAD 0x0
{
ROM_EXEC 0x0
{
vectors.o (Vect, +First)
* (+RO)
}
RAM 0x28000000
{
* (+RW, +ZI)
}
HEAP +0 UNINIT
{
heap.o (+ZI)
}
STACKS 0x28080000 UNINIT
{
stack.o (+ZI)
}
UART0 0x16000000 UNINIT
{
uart.o (+ZI)
}
}
Example of Scatter Loading Script
All other read only code is placed after vector.o
Contain RW and ZI data regions
Heap grows from this address
Stack grows downward from this address
Stack
0x28080000
Heap
RAM
ZI data
RW data
0x28000000
UART
0x16000000
RW data
Main code
Main code
Vectors/init code
Vectors/init code
Load view
Execution view
UNINIT: not zero-initialized by the C lib initialization code
ROM
0x00000000
Example of Scatter Loading Script
ROM/RAM Remap
嵌入式系統架構軟體設計
---using ARM
FLASH 0x24000000 0x4000000
{
FLASH 0x24000000 0x4000000
{
init.o (init, +First)
* (+RO)
}
32bitRAM 0x0000
{
vectors.o (Vect, +First)
* (+RW,+ZI)
}
HEAP +0 UNINIT
{
heap.o (+ZI)
}
STACKS 0x40000 UNINIT
{
stack.o (+ZI)
}
UART0 0x16000000 UNINIT
{
uart.o (+ZI)
}
}
Program code
(RO +RW )
Remapped
after RESET
Program code
(RO +RW )
0x28080000
I/O address
0x16000000
Stack
0x00040000
0x24000000
ROM
UART0
Heap
32bitRAM
ZI data
Aliased copy
of code at
0x24000000
Initialized
RW data
Program code
(RO + RW )
Vectors
Load view
Execution view
0x00000000
嵌入式系統架構軟體設計
---using ARM
Initialize Application
 Initialize nonzero writable data by copying the initializing values
(RW from ROM to ROM) to the writable data region
 Set all writable data of ZI region to zero.
 When the compiler compiles a function called main(), it generates a
reference to the symbol__main to force the linker to include the
basic C run-time system from the ANSI C library.
(The symbol __main is marked as an entry point.)
嵌入式系統架構軟體設計
---using ARM
__user_initial_stackheap()
In /Retarget.c
__value_in_regs struct__initial_stackheap__user_initial_stackheap(unsigned R0,
unsigned SP, unsigned R2, unsigned SL)
{
struct__initial_stackheap config;
config.heap_base = 0x00060000;
config.stack_base = SP;
return config;
}
嵌入式系統架構軟體設計
---using ARM
練習：Build & Trace a ROM Image
 Try example\embedded\embed\embed.mcp
 Building an image by ADS
 Trace code by AXD
嵌入式系統架構軟體設計
---using ARM
Case Study:
Build An Image for Wiscore EVM
 Application:
 7-segment LED test
 Set up Timer 0: Interrupt to flash LED 0
 While loop detect switch & change 7-segment LED number
嵌入式系統架構軟體設計
---using ARM
S3C4510B Initial Memory Map
Power On
0x3FFFFFF
0x3FF0000
Special Function Registers
64 M Bytes
SA[25:0]
ROM bank 0 at 0x0
Each bank is defined
as a 32M space
Undefined Area
0x2000000
ROM/SRAM/FLASH Bank 0 Area
(Non-Accessible)
ROM/SRAM/FLASH Bank 0 Area
(Accessible)
32M
4M Address[21:0]
0x000000
Figure4-2 Initial System Memory Map (After Reset)
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register Base
Register
Offset Address
R/W
Description
Reset Value
SYSCFG
0x0000
R/W
system configuration register
0x37FFFF91
 SYSCFG register determines:
 Start address of the System Manager’s special registers
 Start address of internal SRAM.
• (The total special register space in the system memory map is fixed at 64 K
bytes.)
31 30
S
D
M
26 25
PD_ID
16 15
Special Register Bank
Base Pointer
[15:6] Internal SRAM base pointer
This 10-bit address becomes the upper address of SRAM.
A25 through A16, the remaining SRAM address, and A15
through A0, are filled with zeros.
[25:16] Special register bank base pointer
The resolution of this value is 64K. Therefore, to place the
start address at 1800000H (24M), use this formula:
Setting value = (1800000H/64K)<<16.
2 1 0
W C S
0
E E E
6 5 4 3
Internal SRAM
Base Pointer
CM
0x37FFFF91
0111,1111,1111
27
Special Reg. Base: 3FF,0000
16
嵌入式系統架構軟體設計
---using ARM
NET-Start! EVM Memory Mapping
Figure 3-1 NET-Start! Memory Map
Address Range
0x00000000 to 0x01000000
0x01800000 to 0x01A00000
0x03FE0000 to 0x03FE1FFF
0x03FF0000 to 0x03FFFFFF
Size
16MB
2MB
8KB
64KB
Description
32-bit SDRAM, using DRAMCON0
16-bit Flash bank, using ROMCON0
32-bit international SRAM, used as cache by bootloader
S3C4510 control registers
Figure 3-2 Memory Usage
Address Range
0x00000000 to 0x0000003F
0x00000040 to 0x00007FFF
0x01800000 to 0x0180FFEF
0x0180FFF0 to 0x0180FFFF
0x01810000 to 0x0189FFFF
0x018A0000 to 0x018BFFFF
0x018C0000 to 0x0193FFFF
0x01940000 to 0x019FFFFF
Description
Exception vector table and address constants
Read-write data space for bootloader
Program and read only data space for bootloader
Reserved for Ethernet MAC address
Net-Start! Linux kernel image
Unused (Reserved for kernel expansion)
Initial ramdisk image for NET-Start! Linux kernel
Unused Flash memory
嵌入式系統架構軟體設計
---using ARM
NET-Start! 7-segment LED&LEDs
嵌入式系統架構軟體設計
---using ARM
GPIO Assignments
Figure 2-8 NET-Start! GPIO assignment
GPIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
GPIO_0
GPIO_1
GPIO_IN0
GPIO_IN1
GPIO_RESERVED
GPIO_WATCHDOG_CLK
GPIO_RS485_DRIVER_EN
GPIO_RS485_READ_EN
GPIO_8 / GPIO_EXT_IRQ0
GPIO_8 / GPIO_EXT_IRQ1
GPIO_CTS
GPIO_RI
GPIO_12 / GPIO_EXT_DRQ0
GPIO_RTS
GPIO_14 / GPIO_EXT_DACK1
GPIO_CD
GPIO_LED0
GPIO_LED1
Description
General purpose I/O 0
General purpose I/O 1
User input switch 1 within SW2
User input switch 2 within SW2 [Note]
Not Available
Watchdog timer clock control
RS485 transceiver driver enable
RS485 transceiver read enable
General purpose I/O 8 / External IRQ0
General purpose I/O 9 / External IRQ1
RS232 Clear to Send
RS232 Ringing Indicator
General purpose I/O 12 / External DMA request 0
RS232 Request To Send
General purpose I/O 14 / External DMA acknowledge 0
RS232 Carrier Detect
User Programmable LED D1
User Programmable LED D2
Note: The GPIO_IN1 is used by the bootstrap loader. Selecting the ON position will
force the bootstrap loader to run in the diagnostic mode. Otherwise, the
embedded Linux will be booted up after system power on.
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Registers for I/O Port
IOPMOD
VDD
IOPCON
Port0-Port7
Port8/xINTREQ0
I
I
Port11/xINTREQ3
Port12/nXDREQ0
Port13/nXDREQ1
Port14/nXDACK0
Port15/nXDACK1
Port16/T OUT0
Port17/T OUT1
Alternate Functions
SYSTEM BUS
Output
Latch
IOPDATA
(Write)
IOPDATA
(Read)
Output
Latch
Active
On/Off & Edge
Detection
Interrupt or DMA
Request
IOPCON
Filter
On/Off
IOPCON
Figure 12-1. I/O Port Function Diagram
嵌入式系統架構軟體設計
---using ARM
S3C4510B IOPMOD
Table 12-1. IOPMOD Register
Register
Offset Address
R/W
Description
Reset Value
IOPMOD
0x5000
R/W
I/O port mode register
0x00000000
31
18 17 16 15 14 13 12 11 10 9
8 7 6
5 4 3 2
X X X X X X X X X X X X X X X
[0] I/O port mode bit for port 0
0 = Input
1 = Output
[0] I/O port mode bit for port 1
0 = Input
1 = Output
[0] I/O port mode bit for port 2
0 = Input
1 = Output
[0] I/O port mode bit for port 17
0 = Input
1 = Output
1 0
X X X
嵌入式系統架構軟體設計
---using ARM
S3C4510B IOPCON
31
T
O
E
N
1
30 29 28 27 26 25
23 22
20 19
T
D
D
D
D
O
A
A
R
R
E
K
K
Q
Q
N
1
0
1
0
0
15 14
X
I
R
Q
3
10 9
X
I
R
Q
2
5
4 3
X
I
R
Q
1
[4:0] Control external interrupt request 0 input for port 8 (xlRQ0)
[4] Port 8 for xlNTREQ0
0 = Disable
1 = Enable
[3] 0 = Active Low
1 = Active High
[2] 0 = Filtering Off
1 = Filtering on
[1:0] 00 = Lavel detaction 01 = Rising edge detection
10 = Falling edge detectioon
11 = Both edge detection
Table 12-2. IOPCON Register
Register
Offset Address
R/W
Description
Reset Value
IOPCON
0x5004
R/W
I/o port control register
0x00000000
[9:5] Control external interrupt request 1 input for port 9 (xlRQ1)
(see control external interrupt request 1.)
[14:10] Control external interrupt request 2 input for port 10 (xlRQ2)
(see control external interrupt request 2.)
[19:15] Control external interrupt request 3 input for port 11 (xlRQ3)
(see control external interrupt request 3.)
[22:20] Control external DMA request 0 input for port 12 (DRQ 0)
[22] Port 12 for nXDREQ0
0 = Disable
1 = Enable
[21] 0 = Filtering off
1 = Filtering on
[20] 0 = Active Low
1 = Active High
[25:23] Control external DMA request 1 input for port 13 (DRQ1)
[26]Port 13 for nXDREQ 1
0 = Disable
1 = enable
[24] 0 = Filtering off
1 = Filtering on
[23] 0 = Active Low
1 = Active High
[27:26] Control external DMA acknowledge 0 output for port 14 (DAK0)
[27] Port 14 for nXDACK0
0 = Disable
1 = Enable
[26] 0 = Active Low
1 = Active High
[29:28] Control external acknowledge 1 output for port 15 (DAK1)
[29] Port 15 for nXDACK1
0 = Disable
1 = Enable
[28] 0 = Active Low
1 = Active High
[30] Control timeout 0 for port 16 (TOEN0)
0 = Disable
1= Enable
[31] Control timeout 1 for port 17 (TOEN1)
0 = Disable
1= Enable
2
X
I
R
Q
1
1 0
嵌入式系統架構軟體設計
---using ARM
S3C4510B IOPDATA
Table 12-3. IOPDATA Register
Register
Offset Address
R/W
Description
Reset Value
IOPDATA
0x5008
R/W
I/P port data register
Undefined
31
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
P P P P P P P P P P P P P P P P P
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
[17] I/O port read/write values for ports 17-0 (P0-P17)
NOTE:
The values in the I/O port data register reflect the signal level on the
respective I/O port pins. W hen the ports are configured to output
mode, the bit reflects the ports write value. when the port is
configured to input mode, the bit reflects the ports read value.
Figure 12-4. I/O Port Data Register (IOPDATA)
0
P
0
嵌入式系統架構軟體設計
---using ARM
#define SYS_BASE
#define IOPMOD
#define IOPCON
#define IOPDATA
#define GPIO_LED0
#define GPIO_LED1
Example Code to Control LED
0x03ff0000
((volatile unsigned*)(SYS_BASE + 0x5000))
((volatile unsigned*)(SYS_BASE + 0x5004))
((volatile unsigned*)(SYS_BASE + 0x5008))
0x00010000
0x00020000
void SetLED (int n, int on)
{
int ctr[] = {GPIO_LED0, GPIO_LED1};
if (0 <= n && n< sizeof(ctrl) / sizeof(int))
*IOPDATA = on? (*IOPDATA | ctr[n]) : (*IOPDATA & ~ctrl[n]);
}
嵌入式系統架構軟體設計
---using ARM
S3C4510B Timer
32-Bit Timer Data
Register (TDATAn)
fMCLK
TMOD.TEn
Auto
Re-load
32-Bit Timer Count
Register (TCNTn)
[Down Counter]
TMOD.TMDn
TMOD.TCLRn
PND
INTPND and
INTMSK
Interrupt
Request
Pulse
Generator
TOUTn
Port 16, Port 17
Data Out
IOPCON.TOENn
fTOUT
f TOUT = f MCLK / Timer data value
Interval Mode
Time-out
Time-out
Time-out
fTOUT
Toggle Mode
(Initial TOUTn is 0)
f TOUT = f MCLK / (2 * Timer data value)
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register TMOD
Table 11-1. TMOD Register
Register
Offset Address
R/W
Description
Reset Value
TMOD
0x6000
R/W
Time mode register
32 h00000000
31
6 5
T
C
L
R
1
[0] Timer 0 enable (TE0)
0 = Diable timer 0
1 = Enable timer 0
[1] Timer 0 mode selection (TMD0)
0 = Internal mode
1 = Toggle mode
[2] Timer 0 initial TOUT0 value (TCLR0)
0 = Initial TOUT0 is 0 in toggle mode
1 = Initial TOUT0 is 1 in toggle mode
[3] Timer 1 enable (TE1)
0 = Diable timer 1
1 = Enable timer 1
[4] Timer 1 mode selection (TMD1)
0 = Interv al mode
1 = Toggle mode
[5] Timer 1 initial TOUT 1 value (TCLR 1)
0 = Internal TOUT1 is 0 in toggle mode
1 = Internal TOUT1 is 1 in toggle mode
4 3 2
T T T
D E C
M 1 L
R
1
0
1 0
T T
D E
M 0
0
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register TDATA
TIMER DATA REGISTERS
The timer data registers, TDATA0 and TDATA1, contain a value that specifies the
time-out duration for each timer. The formula for calculating the time-out duration is:
(Timer data +1) cycles.
Table 11-2. TDATA0 and TDATA1 Registers
Register
Offset Address
R/W
Description
Reset Value
TDATA0
TDATA1
0x6004
0x6008
R/W
R/W
Timer 0 data register
Timer 1 data register
0x00000000
0x00000000
0
31
Receive Data
[31:0] Timer 0/1 data value
Figure 11-4. Timer Data Registers (TDATA0, TDATA1)
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register TCNT
TIMER COUNT REGISTERS
The timer count registers, TCN0 and TCNT1, contain the current timer 0 and 1 count
value, respectively, during normal operation.
Table 11-3. TCNT0 and TCNT1 Registers
Register
Offset Address
R/W
Description
Reset Value
TCNT0
TNCT1
0x600C
0x6010
R/W
R/W
Timer 0 counter register
Timer 1 counter register
0xFFFFFFFF
0xFFFFFFFF
0
31
Timer count
[31:0] Timer 0/1 count value
Figure 11-5. timer Counter Registers (TCNT0, TCNT1)
嵌入式系統架構軟體設計
---using ARM
#define TMOD
#define TDATA0
Example Code to Control Timer
*(volatile unsigned*)(SYS_BASE + 0x6000)
*(volatile unsigned*)(SYS_BASE + 0x6004)
void Init_Timer()
{
TDATA0 = 0x17D7840
TMOD = 0x1;
}
//MCLK/25M
//enable timer0 at interval mode
嵌入式系統架構軟體設計
---using ARM
S3C4510B Interrupt Controller
Table 13-1, S3C4510B Interrupt Sources
Index Values
Interrupt Sources
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2
I C-bus interrupt
Ethernet controller MAC Rx interupt
Ethernet controller MAC Tx interupt
Ethernet controller BDMA Rx interupt
Ethernet controller BDMA Tx interupt
HDLC channel B Rx interrupt
HDLC channel B Tx interrupt
HDLC channel A Rx interrupt
HDLC channel A Tx interrupt
Timer 1 interrupt
Timer 0 interrupt
GDMA channel 1 interrupt
GDMA channel 0 interrupt
UART 1 receive and error interrupt
UART 1 transmit interrupt
UART 0 receive and error interrupt
UART 0 transmit interrupt
External interrupt 3
External interrupt 2
External interrupt 1
External interrupt 0
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register INTMOD
Table 13-2. INTMOD R egister
Register
Offset Address
R/W
Description
Reset Value
INTMOD
0x4000
R/W
Interrupt mode register
0x00000000
31
INTMOD
21 20 19 18 17 16 15 14 13 12 11 10 9
X X X X X X X X X X X X
8 7
X X
6
X
5
X
4
X
3 2
1 0
X X X X
[20£º0] Interrupt mode bits
NOTE:
Each of the 21 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source.
When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM7TDMI core in FIQ
(fast interrupt) mode. Otherwise, it is processed in IRQ mode (normal interrupt).
The 21 interrupt sources are mapped as follows:
[20] 12C interrupt
[19] Ethernet controller MAC Rx interupt
[18] Ethernet controller MAC Tx interupt
[17] Ethernet controller BDMA Rx interupt
[16] Ethernet controller BDMA Tx interupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
[9] GDMA channel 1 interrupt
[8] GDMA channel 0 interrupt
[7] UART1 receive and error interrupt
[6] UART1 transmit interrupt
[5] UART0 receive and error interrupt
[4] UART0 transmit interrupt
[3] External interrupt 3
[2] External interrupt 2
[1] External interrupt 1
[0] External interrupt 0
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register INTPND
INTERRUPT PENDING REGISTER
The interrupt pending register. INTPND contains interrupt pending bits for each interrupt
source. This register has to be cleared at the top of an interrupt service routine.
Table 13-3. INTPND Register
Register
Offset Address
R/W
Description
Reset Value
INTPND
0x4004
R/W
Interrupt pending register
0x00000000
31
INTPND
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X X
[20£º0] Interrupt pending bits
NOTE: Each of the 21 bits in the interrupt mode pending register, INTPND, corresponds to
an interrupt source. W hen an interrupt request is generated, its pending bit is set
to 1. This service routine must then clear the pending condition by writing a 1 to
the apropriate pending bit at start. The 21 interrupt sources are mapped as
follows:
[20] 12C interrupt
[19] Ethernet controller MAC Rx interupt
[18] Ethernet controller MAC Tx interupt
[17] Ethernet controller BDMA Rx interupt
[16] Ethernet controller BDMA Tx interupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register INTMSK
Table 13-4. INTMSK Register
Register
INTMSK
31
Offset Address
0x4008
R/W
R/W
Description
Interrupt mask register
Reset Value
0x003FFFFF
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X X
INTMSK
[20£º0] Individual interrupt mask bits
NOTE:
Each of the 21 bits in the interrupt mask register: INTMSK (except for the global mask
bit, G) corresponds to an interrupt source. When a source interrupt mask bit is 1, the
interrupt is not serviced by the CPU when the corresponding interrupt request is
generated. If the mask bit is 0, the interrupt is serviced upon request. And if global mask
bit (bit 21) is 1, no interrupts are serviced. (Howerver, the source pending bit is set
whenever the interrupt is generated.) After the global mask bit is cleared, the interrupt is
serviced. The 21 interrupt source are mapped as follows:
[20] 12C interrupt
[19] Ethernet controller MAC Rx interupt
[18] Ethernet controller MAC Tx interupt
[17] Ethernet controller BDMA Rx interupt
[16] Ethernet controller BDMA Tx interupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
[9] GDMA channel 1 interrupt
[8] GDMA channel 0 interrupt
嵌入式系統架構軟體設計
---using ARM
S3C4510B Special Register INTOFFSET
 INTERRUPT OFFSET REGISTER
 The interrupt offset register, INTOFFSET, contains the interrupt offset
address of the interrupt, which has the highest priority among the
pending interrupts.
 The content of the interrupt offset address is “bit position value of the
interrupt source <<2”.
 If all interrupt pending bits are “0” when you read this register, the return
value is “0x00000054”.
Table 13-6 INTOFFSET Register
Register
INTOFFSET
INTOSET_FIQ
INTOSET_IRQ
Offset
Address
0x4024
0x4030
0x4034
R/W
R
R
R
Description
Interrupt offset register
FIQ Interrupt offset register
IRQ Interrupt offset register
0x0000,0054>>2=21
=Total interrupt
Reset Value
0x00000054
0x00000054
0x00000054
嵌入式系統架構軟體設計
---using ARM
#define INTMOD
#define INTPND
#define INTMSK
#define INTOFFSET
Example Code for Timer0 Interrupt Control
*(volatile unsigned*)(SYS_BASE + 0x4000)
*(volatile unsigned*)(SYS_BASE + 0x4004)
*(volatile unsigned*)(SYS_BASE + 0x4008)
*(volatile unsigned*)(SYS_BASE + 0x4024)
void interrupt_InitMask()
{
INTMSK = 0x1FFBFF;
INTPND = 0x0;
}
lrq handler.s
STMFD
LDR
LDR
MOV
MOV
MOV
LDR
STR
LDMFD
sp!, {r1-r3}
r3, =INTOFFSET
r2,[r3]
r2,r2,LSR#2
r1,#0x1
r1,r1,LSL r2
r3,=INTPND
r1,[r3]
sp!,{r1-r3}
// enable Timer0 interrupt
Timer0 IRQ
INTOFFSET = 0b101000
r2 = 0b101000>>2 = 0b1010 = 10
嵌入式系統架構軟體設計
---using ARM
 Commands:












HELP-help
UNIT – Set access unit
DUMP – Memory dump
COPY- Memory copy
FILL – Fill memory
POKE – Poke memory
PEEK – Peek memory
TX – Send XMODEM file
RX – Receive XMODEM file
GO – Execute binary
INFO – Print system information
SWITCH – Switch mode
 Load image:






Select SW2 to OFF position
Press RESET button
Terminal set: bound rate 19200,8N1
RUN>rx 0x10000
RUN>copy 0x10000 0x20000 0x1810000
RUN>go 0x1810000
Use Net-Start! Bootloader
嵌入式系統架構軟體設計
---using ARM
練習：Timer 2
 根據前面的CASE，增加Timer 2功能， 讓Timer 2 控制另一顆LED.
嵌入式系統架構軟體設計
---using ARM




ARM Developer Suite Version 1.2 Developer Guide
ARM Developer Suite Version 1.2 Linker and Utilities Guide
Wiscore Net! Start user Guide
SAMSUNG S3C4510B User Manual
Reference