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TFT LCD AIM SPICE
P92943013 / 梁亦中
P91943014 / 方貴弘
Past History of SPICE
• SPICE : Simulation Program with Integrated Circuit Emphasis
• 1968 : Ron Rohrer Berkeley,Larry Nagel CANCER
• 1970 : SPICE1(Fortran)
Shell
• 1975 : SPICE2(Fortran)
• 1980 : SPICE3(C Language)
• 1980~Now :
HSPICE
PSPICE
Kernel
AIM-SPICE (AIM)
HSPICE
PSPICE
Berkeley
Smart-SPICE (Silvaco)
SPICE
Eldo (Mentor)
Spectre (Cadence)
SPICE Algorithms
Principle : Kirchhoff’s Law
N
 In  0
node
n 1
N
V
n 1
n
0
Numerical analysis : Newton Method
Analog Circuit Design Flow
Schematic edit
Circuit simulation
SPICE
Schematic driven layout
Layout
-Laker
DRC/LVS
-Calibre
Device model extraction
1. TEG data analysis
2. Curve fitting
3. Process characterization
No
Yes
Parasitic R/C Extractor
-Calibre RCX
Post simulation
SPICE
GDS II / Mask
AIM SPICE Parameter Extract_1
TFT LCD Test Mask IV Curve
IdVd Curve
Vg = 5V,10V,15V,20V,30V
IdVg Curve
Vd = 1V,4V,7V,10V,13V
Modeled
Measured
AIM SPICE Parameter Extract_2
Below Threshold
Hole-Induced
Leakage Current
10 -4
10 -4
10 -5
10 -5
10 -5
10 -6
10 -6
10 -6
10 -7
10 -8
10 -9
10 -10
Drain cu rren t [A]
10 -4
Drain cu rren t [A]
Drain cu rren t [A]
Above Threshold
10 -7
10 -8
10 -9
10 -10
10 -7
10 -8
10 -9
10 -10
10 -11
10 -11
10 -11
10 -12
10 -12
10 -12
10 -13
10 -13
-10
-5
0
5
10
15
Gate-source voltage [V]
I ds,lin   FET
-5
0
5
10
15
-10
Gate-source voltage [V]
W
Cox (Vg  VT )Vds
L
Vg  VT  Vds 
 FET  n 

V AA


10 -13
-10

Extract
Parameter
  t   VgFBe   i  
W
I sub  q n Vds nso  m  
 
L
  di   V2    s  
-5
0
5
10
15
Gate-source voltage [V]
  1
1 
I hl  I min  exp El 


  Vth Vtho  
 Vgs 
V


 exp ds   1  exp

 VGL 
  VDSL  
( 2Vs /Ve )
AIM SPICE Parameter Extract_3
Pixel Equal Circuit & RC Calculation
Cgate =((Cst*Clc)/(Cst + Clc) + Cgs + Cgs_coup + Cdg cross + Cgate_com)*1280*3
Rgate =(ρ * L1/W1)*1280*3
Cdata =Cgd + Cdg cross + Cdata_com + Cpixel_data_coup)*1024
Rdata=(ρ * L2/W2)*1024
Cpixel = Cgs + Cgs_coup + Clc + Cst + Cpixel_data_coup
L1
Data Line
the N-1th
Data Line
the N th
1
5
W1
Gate Line
the (N-1)th
2 C lc
1 C st(on gate)
9 C pixel_data
coup(own)
6 C data_com
2
6
( lc )
10 C pixel_data
coup(next)
9
8
Gate Line
the Nth
8 C gs_coup
10
3 C gs
5 C gate_com
4 C gd
7 C dg cross
3
4
7
W2
L2
Using Pi(π) Model to Simulated
We using 4 π Model to simulated one gate line and data line
R
One πmodel
C
1
1
1
1
 C gate  C3 _ 0   C17 _ 0   C4 _ 0   C20 _ 0  C5 _ 0
8
2
2
2
1
1
1
 C10 _ 0   C23 _ 0   C11 _ 0   C26 _ 0  C12 _ 0
2
2
2
1
 Rgate  R3 _ 17  R17 _ 4  R4 _ 20  R20 _ 5
4
 R10 _ 23  R23 _ 10  R10 _ 26  R26 _ 12
1
1
1
 Cdata  C1 _ 0   C14 _ 0   C2 _ 0
8
2
2
1
 Rdata  R1 _ 14  R14 _ 2
4
Panel Equal Circuit of Simulation
1
If Resolution = 1280*1024
Node 3 = Sub_pixel (0,512)
Node 4 = Sub_pixel (1920,512)
Node 5 = Sub_pixel (3840,512)
Signal in
1
2
6
7
8
14
V
Gate n-1 Pulse
Driving Direction
2
10
11
V
12
23
26
Gate n Pulse
3
4
5
V
17
6
20
7
9
8
9
9
SPICE Program Description 1 - Basic Definition
(Device+Name)
Device:
D: Diode
C: Capacitance
I: Independent
Current Source
J: JFET
M: MOS
Q: BJT
R: Resister
V: Independent
Current Source
Node Value / Parameter
ex: Rgate 1 3 25k
Cgate 1 3 25p
Vgate 1 3 25V
M1 2(D) 3(G) 6(S) 0(GND) Model()
SPICE Program Description 2 - Basic Definition
Dot Command
Format =>
. command
.DC
.END
.IC
.MODEL
.PLOT
.PRINT
.TRAN
直流掃描
檔案結束
設定起始電壓電流
MODEL宣告
輸出圖形
輸出數值
暫態分析
SPICE Program Description 3 – Power definition
VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u vgh 35.32u vgl 150u vgl
VSIG1 2 0 PULSE (vdl vdh 12.5u 1n 1n 12.499u
25u)
V1 V2 start rise fall pulse width period
V2
V1
VCOM2 9 0 5V
5V DC voltage source
SPICE Program Description 4 - Example 1
*** Simulation of One Gate Delay by AIM-Spice
***
.param vgh=27V vgl=-6V vgc=-6V
.param gpi_r=1.176k gpi_c=24.27p
.param gpx_r=0.3k
*** PI-g2
RGATE21 4 7 gpi_r
RGATE22 7 5 gpi_r
CGATE21 4 0 gpi_c
.param length=9u width=18u
VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh
+35.31u vgh 35.32u vgl 150u vgl
.IC V(10)=vgl V(3)=vgl
***GATE DELAY 0
***GATE DELAY 2
3
0
CGATE22 7 0 gpi_c*2
6
4
7
5
CGATE23 5 0 gpi_c
.TRAN 1.000000e-07 100u
.PLOT TRAN V(3) V(4) V(5)
*** Drive IC
.END
RGATE01 0 3 gpx_r
CGATE01 0 3 2.5p
30.0
CGATE02 0 10 2.5p
RGATE11 3 6 gpi_r
RGATE12 6 4 gpi_r
CGATE11 3 0 gpi_c
CGATE12 6 0 gpi_c*2
CGATE13 4 0 gpi_c
'v(4)'
'v(5)'
*** PI-g1
Y Axis Title [V]
***GATE DELAY 1
'v(3)'
20.0
10.0
0.0
-10.0
0.0u
20.0u
40.0u
60.0u
time [sec]
80.0u
100.0u
SPICE Program Description 5 - Model - 1
General form:
MXXXXXXX ND NG NS NB MNAME <L=VALUE> <W=VALUE> <AD=VALUE>
+ <AS=VALUE> <PD=VALUE> <PS=VALUE> <NRD=VALUE>
+ <NRS=VALUE> <OFF> <IC=VDS,VGS,VBS> <TEMP=T>
a-Si TFT in SMART SPICE
.MODEL •TFT •NTFT •
(LEVEL = 35, ******* )
a-Si TFT in AIM SPICE
.MODEL •TFT •NMOS •
(LEVEL = 15, ******* )
SPICE Program Description 6 - Model - 2
Example of a-Si TFT Description by AIM Spice
M1 2 3 6 0 TFT L=length W=width
.MODEL TFT NMOS ( LEVEL = 15 TOX = 3.5E-7
+TNOM = 27
VTO = 1.6
+ALPHASAT= 0.8101843
DEFO = 0.598965
DELTA = 9.2
+EL
= 1.1
EMU = 0.06
EPS = 11
+EPSI = 4.7
GAMMA = 0.3709371
GMIN = 3.98107E22
+IOL = 6.30957E-14 KASAT = 1E-3
KVT = -0.036
+LAMBDA = 0
M
= 1.1733413
MUBAND = 1E-3
+SIGMAO = 3.16228E-15 VO
= 0.37
VAA = 3.117726E4
+VDSL = 15
VFB = -2.41736
VGSL = 100
+VMIN = 0.797118
CGDO = 0.6n
CGSO = 0.6n )
SPICE Program Description 7 - Example 2
*** Simulation of One Pixel By AIM-Spice ***
.param vgh=27V vgl=-6V
.param vdl=1V vdh=10V
.param gpx_r=0.3k
.param lcc=0.179p csc=0.164p cgsc=0.0078p
.param length=9u width=18u
VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u
+ vgh 35.32u vgl 150u vgl
VGATE2 10 0 vgl
VSIG1 2 0 PULSE (vdh vdl 12.5u 1n 1n 12.499u 25u)
VCOM2 9 0 5V
.IC V(10)=vgl V(3)=vgl V(9)=5V
.IC V(2)=vdh
.IC V(6)=vdl
RGATE01 0 3 gpx_r
CLC1 6 9 lcc
Cs1 6 10 csc
CGS1 3 6 cgsc
***TFT***
M1 2 3 6 0 TFT L=length W=width
* SiOx thickness 3500A
.model TFT NMOS(level=15 alphasat=0.715 defo=0.6 delta=5
emu=0.02
+ el=0.1 eps=11 epsi=4.7 gamma=0.535 gmin=1e+023 iol=2.8e-012
+ kvt=-0.01 lambda=0.001 m=1.2 muband=0.001 rd=220000 rs=220000
+ sigmao=5e-014 tnom=27 tox=3.5e-007 vaa=2400 vdsl=30 vfb=-5.38
+ vgsl=50 vmin=0.3 vo=0.29 vto=1.8 )
.TRAN 1.000000e-07 100u
.PLOT TRAN V(2) V(3) V(6)
.END
30.0
'v(2)'
'v(3)'
'v(6)'
CGATE01 0 3 2.5p
CGATE02 0 10 2.5p
Y Axis Title [V]
RGATE02 0 10 gpx_r
20.0
10.0
0.0
-10.0
0.0u
20.0u
40.0u
60.0u
time [sec]
80.0u
100.0u
SPICE Output Node Waveform
What can we gain from this Waveform Chart?
• Gate Delay
• Charging Capability
• Feedthrough Voltage
Y Axis Title [V]
29.3
'v(1)'
'v(2)'
'v(3)'
'v(5)'
'v(6)'
'v(7)'
'v(8)'
'v(10)'
'v(12)'
14.5
-0.2
-15.0
3.9u
17.7u
31.6u
time [sec]
45.4u
Gate Delay Simulation Data
17” Gate Delay at charge time 10.3us
Gray level = L0 (black)
30
Start
End
25
20
15
10
5
0
-5
-10
Gate Delay(at Vg=0V)
Measured=1.2us
Simulated=1.2us
22
24
26
28
30
32
34
36
38
40
42
44
Other Case about SPICE Simulation_1
19” Gate Pulse Cut (Cs on Com)
Y Axis Title [V]
30.0
'v(1)'
'v(2)'
'v(3)'
'v(5)'
'v(6)'
'v(7)'
'v(8)'
20.0
10.0
0.0
-10.0
0.0u
50.0u
100.0u
time [sec]
150.0u
Other Case about SPICE Simulation_2-1
dVcom = (dVp_P + dVp_N)/2
Other Case about SPICE Simulation_2-2
 Modify = Simulation * 1.5
17 inch
Smart SPICE & Measurement Comparison
300.0
dVcom (mV)
250.0
200.0
150.0
Measure
Simulation
Modify
100.0
50.0
0.0
1
2
3
4
5
Position
6
7
8
9
Other Case about SPICE Simulation_3
Cpd Coupling Effect Simulation
LCD Circuit for Smart Spice ( Orcad )
LCD Pixel Circuit for Smart Spice
Pixel Capacitance
Clc=0.139pF
Cst=0.229pF
Cgs=0.011pF
Cpd_L=0.012pF
Cpd_R=0.010pF
Rlc=10E12ohm
Other Capacitance
Cgc=0.009pF
Cdc=0.022pF
Cgd=0.056pF
The End