Transcript Title Page Layout - UCL Discovery

HIGH SPEED, PLUGGABLE OPTICAL BACKPLANE
CONNECTOR TECHNOLOGY
Richard Pitwon, Ken Hopkins, Dave Milward
Xyratex Technology Ltd
David R. Selviah, Ioannis Papakonstantinou
Kai Wang, F. Anibal Fernández
University College London (UCL)
International Symposium on Photonic
Packaging
Electrical Optical Circuit Board and Optical
Backplane
organized by Fraunhofer IZM & VDI/VDE-IT
Munich, Germany
November 2006
THE STORLITE PROJECT
2
Purpose
Duration
British government funded initiative to
investigate incorporation of optical
backplanes into high bandwidth systems
and develop solutions
June 2003 – November 2005
Xyratex
University College London
Exxelis Ltd
Investigation into optical backplane
connector technology and prototype
solution development
Investigation into performance
enabling polymer waveguide
structures and characterisation
Optical PCB
manufacture
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RESEARCH OBJECTIVES
•
•
Investigation of current state of the art in optical PCB technology research
•
Polymeric waveguide fabrication and characterisation
•
Optical PCB Design Rules
Investigation into low-cost technology drivers
•
•
Development of prototype solutions
•
•
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Method of pluggable daughtercard connection to an optical backplane
Parallel optical transceiver and pluggable optical backplane connector
Development of prototype demonstration assembly
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RESEARCH AND DEVELOPMENT OVERVIEW
•
High speed parallel optical transceiver
•
Opto-mechanical registration interface
•
Low-cost optical backplane connection
mechanism
•
Low cost precision optical alignment and
assembly method
4
•
Optical PCB interface coupling method
•
Prototype demonstration unit
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HIGH BANDWIDTH BACKPLANE ENVIRONMENTS
16 Drive EBOD Storage System
12 Drive SBOD Storage System
48 Drive RAID Storage System
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HIGH BANDWIDTH BACKPLANE
Dual Port
Disk Drives
Power
Module
Air Flow
Channels
High Speed
Connectors
To Controllers
Multi Layer
Interconnect Backplane
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Controller
Module
BACKPLANE ENGAGEMENT MODEL
Copper layers to carry power,
Embedded optical channels to
Orthogonal daughtercard
control signals and low speed
carry high speed serial signals
engagement to backplane
signals
between cards
High bandwidth backplane
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PROPOSED COUPLING PRINCIPLE
Daughtercard
Surface emitting photonics used
on daughtercard interface
Butt-coupling scheme allows for
minimum number of
intermediary optical interfaces
Optical Waveguides
VCSEL
Copper Traces
Backplane
Copper Planes
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PARALLEL OPTICAL TRANSCEIVER DESIGN
•
Quad duplex parallel optical transceiver
•
10.3 Gbps per channel (82 Gb/s aggregate
bandwidth)
•
Electronic daughtercard connector
•
Flexible and rigid PCB sections
•
Optical backplane interface
Active opto-mechanical
coupling interface
Rigid optical
interface
Rigid base section
Electronic
Flexible mid-section
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connector
PHOTONIC INTERFACE DESIGN
PIN Array
Source: Microsemi Corporation
VCSEL Array
Source: ULM Photonics GmbH
MT compatible
interface
GRIN Lens Array
Source: GRINTech GmbH
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OPTOELECTRONIC PCB WITH MT – SOCKET INTERPOSER
MT-socket
interposer
(a)
(b)
Ceramic lens holder
MT-plug
MT-pins
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MT - SOCKET INTERPOSER ON THE TOP OF BACKPLANE
0.35650 ± 0.00001
0.66 ±
0.01
3.8870 ± 0.0001
0.02 mm
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3.8825 ± 0.005
mm
0.25 mm
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0.53125 mm
ACTUAL ALIGNMENT OF THE COMPONENT
registration features
waveguides
3886 µm
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SUPPORT DAUGHTERCARD DESIGN
4 Port 10 GbE LAN Physical Relay board
Transceiver receptacle
PCB material
Rogers 4350 on
outer layers
Host interface
4 XFP ports
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CHARACTERISATION SETUP
Physical layer relay
MT patchcord for
board
stand alone testing
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•
Test traffic: 10 GbE LAN (10.3 Gbps)
•
VCSEL bias current:
11.91 mA
•
VCSEL modulation current:
9.8 mA
•
Divergence:
25°
•
Output optical power:
0.43 mW
•
Average optical jitter:
31.2 ps (Pk – Pk)
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CONNECTOR MECHANISM
Principal Function
Elevation and retraction of optical interface
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ALIGNMENT METHOD BASED ON MT CONCEPT
daughtercard
x
MT-pin
z
θ
φ
y
4 PD array
4 VCSEL array
array of
backplane
12waveguides
MT-pin
MT-holes
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POLYMER OPTICAL WAVEGUIDE TECHNOLOGY
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POLYMER WAVEGUIDE CHARACTERISTICS
Waveguide Material
UV-curable polymeric acrylate (Truemode®)
Propagation loss @ 850 nm: 0.04 dB/cm
Heat degradation resilience:
up to 350°C
Waveguide properties
Size:
70 µm x 70 µm
Core index:
1.556
Cladding index:
1.526
Numerical aperture: 0.302
Waveguide Array
Centre to centre pitch: 250 µm
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Passive Electrical Backplane
Separate passive
electrical backplane
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard Guide Features
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard Power Supply
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard to Optical Backplane Coupling Evaluation
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Optical Backplane Integration
Separate optical PCB
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Complete Demonstration Unit
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TEST AND CHARACTERISATION
Optical Coupling Characterisation
Test traffic: 10 GbE LAN (10.3 Gbps)
Arrangement:
Active connector – waveguide - patchcord
Wavelength: 850 nm
Multimode MT fibre
Reference Signal – No Waveguide
patchcord
Jitter
:
Relative Loss:
0.34 UI
0 dB
10 cm Waveguide with Isapropanol
Jitter
0.36 UI
Relative Loss
4.5 dB
10 cm Waveguide – Diced and Polished
Jitter
0.56 UI
Relative Loss
6.9 dB
10 cm Waveguide – Diced Only
Active prototype
Jitter
0.89 UI
Relative Loss
connector
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7.9 dB
TEST AND CHARACTERISATION
High Speed Network Link Evaluation
Arrangement:
Test traffic source (10 GbE LAN)
Fibre cable
XFP Port 1 (Rx)
Daughtercard 1
Connector 1 (Tx)
Optical PCB
Connector 2 (Rx)
Daughtercard 2
XFP Port 2 (Tx)
Fibre cable
Traffic Capture
Bit Error Rate < 10-12
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CONTOUR MAP OF VCSEL AND PD MISALIGNMENT
(a) Contour map of relative
insertion loss compared to the
maximum coupling position for
VCSEL misalignment at z = 0.
(b) Same for PD misalignment at
z = 0. Resolution step was Δx
= Δy = 1 µm.
 Dashed rectangle in the middle of the maps corresponds to the expected relative
insertion loss according to the calculated misalignments along x and y in text slides.
 The minimum insertion loss was 4.4 dB, corresponded to x = 0, y = 0, z = 0
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TOLERANCES ALONG X, Y AND Z FOR CONNECTOR COMPONENTS
X
y
Z
MT-plug
3 μm (pin-to-pin)
3 μm (pin-to-GRIN)
________
MT-socket
3 μm (hole-to-hole)
3 μm (hole-to-waveguide)
________
OPCB features
+2.5 μm (increase in
registration wall-to-wall
spacing due to
overexposure)
2.5 μm (due to 5 μm extra
spacing between feet of
interposer)
1 μm (core thickness
control)
+10 μm (accuracy of dicing in
respect to the dicing lines
on the board)
+2.5 μm (backstop shift due to
overetching)
Tolerance of MT
interposer socket to
waveguides
8 μm or 3 μm if
overexposure widening is
known and reproducible
Combined tolerance
of VCSEL and PIN to
waveguides
11 μm or 6 μm if
overexposure widening is
known and reproducible
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4 μm
+12.5 μm or +10 μm if
overexposure widening is
known and reproducible
7 μm
+12.5 μm or +10 μm if
overexposure widening is
known and reproducible
RELATIVE INSERTION LOSS OF VCSEL AND PD
AS THEY MOVE AWAY FROM THE OPCB WAVEGUIDES.
4
Insertion Loss (dB)
3.5
VCSEL
3
Photo Detector
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
axial distance z (μm)
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140
160
180
200
CROSSTALK MEASUREMENT 1
PD
Relative power at 0th waveguide (dB)
0
-5
-10
0th
1st
2nd
3rd
4th
5th
6th
0
250
500
750
1000
1250
1500
-15
-20
-25
-30
-35
-250
VCSEL
x (m)
Power received at the end of 0th waveguide as a function of the lateral distance of the
VCSEL from its center. The boundaries and the centers of the waveguides on the
backplane are marked. In the cladding power drops at a rate of 0.011 dB/µm
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CROSSTALK MEASUREMENT 2
6th
35
(b)
5th
4th
30
3rd
2nd
SXR (dB)
25
1st
20
15
10
5
0
-70
-50
-30
-10
0
10
x (m)
30
50
70
Signal-to-cross-talk (SCR) levels that 0th waveguide experiences from its adjacent
waveguides.
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CROSSTALK MEASUREMENT 3
25
1 and 4 waveguides in connector
2 and 3 waveguides in connector
SCR (dB)
20
15
10
5
0
-80
-60
-40
-20
0
x (m)
20
40
60
80
SCR experienced by waveguides number 1 and 4 and of waveguides number 2 and 3
from the array of four in the connector if all are in use. Dashed-dot lines determine the
boundaries of the maximum expected cross-talk based on current connector
tolerances.
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STABILITY TESTING OF THE MT – SOCKET INTERPOSER 1
Insertion loss and signal to cross-talk (SCR) as a function of mating cycle for 75
engagements.
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STABILITY TESTING OF THE MT – SOCKET INTERPOSER 2
Histogram of insertion loss
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THE CANDEO PROJECT
Purpose
Industrial collaborative effort to develop
commercial technology drivers for optical
backplane and connector technology and
drive the proliferation of optical backplane
technology into the industrial sector
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Xyratex
Samtec
Commercial development of
proprietary parallel optical
transceiver technology
Commercial development of optical
backplane engagement mechanism
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CANDEO CURRENT STATUS
Phase I
(currently underway)
•
High speed parallel optical transceiver design modified for
commercial design
•
Single stage optical backplane engagement mechanism
developed
•
Commercial form factor module designed and developed
•
First mechanical prototype on exhibition by Samtec and Xyratex
at Electronica 2006, Samtec booth 419 in Hall B4
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INTEGRATED OPTICAL AND ELECTRONIC PCB MANUFACTURING
Purpose
To
compare
multimode,
polymer
waveguide
manufacture techniques for large area optical
backplanes and to develop design rules.
Academic Partners
University College London (UCL) – Waveguide design, modelling, measurement
Heriot-Watt University – Direct UV laser waveguide fabrication
Loughborough University – Laser ablation, surface treatment, printing waveguide
fabrication, flip-chip assembly
Industrial Partners
Xyratex – End user and project manager
BAE Systems – End user
Renishaw – End user
Exxelis – Polymer chemistry, lithographic waveguide fabrication
Cadence – PCB layout tools
Rsoft Design – Optical modeling tools
Xaar – print head technology
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SUMMARY
Xyratex White Papers
• An Optical Backplane Connection System with
Pluggable Active Board Interfaces
(available from Xyratex website)
• Pluggable Optical Backplane Connector Technology
(available)
• Optical vs Copper Cost and Performance Evaluation
(pending)
www.xyratex.com
Intellectual Property
7 patent applications related to optical PCB interconnect
and communication structures and methodologies
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SUMMARY
UCL Publications (available from UCL website)
Papers published on waveguide devices
• Sources misalignment x, y, z
• Detector misalignment x, y, z
• Straight tapered waveguide
• Bends
• Propagation loss
• Thermal optics switch
• Power splitter
• Precision low cost alignment
www.ee.ucl.ac.uk/%7Eodevices/
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Thank You for Your Attention
Acknowledgements
Richard C A Pitwon
Senior Photonics Engineer
Ken Hopkins
UK Department of Trade and Industry
EPSRC
Hardware Architect
Dave Milward
Development Manager
E-mail: [email protected]
David R Selviah
F. Anibal Fernández
Senior Academics
Ioannis Papakonstantinou
Postgraduate Researcher
Kai Wang
Research Fellow
E-mail: [email protected]
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Exxelis
Dr Navin Suyal
Prof. Frank Tooley