Transcript Document

Princess Nora University
Faculty of Computer & Information Systems
Computer science Department
Operating Systems
(CS 340 D)
Dr. Abeer Mahmoud
(Chapter-8)
Memory Management
Strategies
Chapter 8: Memory Management
Strategies
1. Background
2. Swapping
3. Contiguous Memory Allocation
4. Paging
5. Structure of the Page Table
6. Segmentation
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OBJECTIVES:
 To provide a detailed description of various ways of organizing
memory hardware
 To discuss various memory-management techniques, including
paging and segmentation
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Overview
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Overview

Memory is central to the operation of a modern computer system.

Memory consists of a large array of words or bytes, each with its
own address

Selection of a memory-management method for a specific system
depends on many factors, especially on the hardware design
of the system.
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Basic Hardware



Main memory , registers and cash are ONLY storage CPU
can access directly
Program must be brought (from disk) into memory and
placed within a process for it to be run
Huge problem because
of the frequency of
memory accesses.
Direct storage access time:
 Register access in one CPU clock (or less)
 Main memory can take many cycles (i.e. slowly)
 Solution: Cache (fast memory) sits between main
memory and CPU registers
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Basic Hardware

Protection of memory:
 Protection of memory is necessary to ensure correct
operation
 Types of Protection
1. protect the operating system from access by user
processes
2. protect user processes from one another.
 This protection must be provided by the hardware & can be
implemented in several ways.
 One method  : use Base
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and Limit Registers
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Basic Hardware (Cont.)
Base and Limit

We need to make sure that each process has a separate
memory space….How???
 Main idea: we need to determine the range of legal
addresses that can be accessed only by the process.
 We can provide this protection by using two registers (base
& limit)
 The base register>> holds the physical address of the
first byte in the legal range.
 The limit register >> holds the size of the range.
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Basic Hardware (Cont.)
 Example: If the base register holds
300040 and the limit register is
120900….what is the range of legal
addresses ??
 The program can legally access all
addresses from 300040 through 420939
(inclusive)
 NOTE: Last physical address
= base + limit -1
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Basic Hardware (Cont.)

How base & limit registers help to provide memory
protection??

By applying (2) procedures:
 Procedure (1): The CPU hardware compare every
address generated in user mode with the registers.
 Procedure (2): restrict the ability to load base &
limit registers only to OS..
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Basic Hardware (Cont.)

Procedure (1): The CPU hardware compare every address generated
in user mode with the registers.


If (CPU generated address ≥ base) & (CPU generated address <
base +limit) …
 Then …..the CPU generated address is legal and allowed to
access the memory
 Else…… the CPU generated address is illegal and NOT allowed
to access the memory…..(causing a trap (/error) to OS)
This scheme prevents a user program from (accidentally or
deliberately) modifying the code or data structures of either the
operating system or other users…..(solution to protection problem)
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Basic Hardware (Cont.)
Hardware address protection with base and limit registers
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Basic Hardware (Cont.)
 Procedure (2): restrict the ability to load base & limit
registers ONLY to OS.



This restriction applied by using a special privileged instruction.
Since privileged instructions can be executed only in kernel
mode, and since only the operating system executes in kernel
mode…..So, ONLY the operating system can load the base and
limit registers.
This scheme allows the operating system to change the value of
the registers but prevents user programs from changing the registers’
contents.
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Address Binding

Address binding( or relocation): The process of
associating program instructions and data to physical memory
addresses

A user program will go through several steps -some of which
may be optional-before being executed ….. steps are:
1. Compiling
2. Linking
3. Execution
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Address Binding


Addresses may be represented in different ways during
these steps.
o
Addresses in the source program are generally symbolic
(such as count, sum).
o
A compiler will typically bind these symbolic addresses to
re-locatable addresses (such as "14 bytes from the beginning of this module").
o
The linkage editor or loader will in turn bind the relocatable addresses to absolute addresses (physical address)
(such as 74014).
Each binding is a mapping from one address space to another.
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Address Binding (cont.)
Multistep processing of a user program.
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Logical vs. Physical Address Space

Logical/virtual address: address generated by CPU
Physical address: address seen by memory hardware

Compile-time / load-time binding

logical address = physical address

Run-time binding
logical address ≠ physical address
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Logical vs. Physical Address Space


Logical address space: is the set of all logical addresses generated
by a program
Physical address space: is the set of all physical addresses
corresponding to these logical addresses.

MMU (Memory-Management Unit ): h/w device that maps virtual
addresses to physical addresses at run time

Different methods of address mapping (/memory management
strategies):
Continuous memory allocation
Paging
segmentation
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Simple Address Mapping Method

For NOW, we illustrate address mapping with a simple MMU
scheme:

The base register is now called a relocation register.

Basic methodology
Physical address= logical address + relocation register
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Example of Simple Address Mapping
Method
 Base
register contains
14000
If logical address =0 then
Physical address=
0+14000=14000
o If logical address =346
Physical address=
346+14000=14346
o


The user program never sees the real physical addresses. The user
program deals with logical addresses.
MMU converts logical addresses into physical addresses.
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Swapping
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Swapping

Swapping is a mechanism in which a process can be swapped
temporarily out of main memory to a backing store , and then
brought back into memory for continued execution.

Backing store is a usually a hard disk drive or any other
secondary storage which fast in access and large .
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Swapping (Cont.)

How swapping performed???
 The system maintains a ready queue consisting of all processes
whose memory images are on the backing store or in memory
and are ready to run.

Whenever the CPU scheduler decides to execute a process,
it calls the dispatcher.

The dispatcher checks to see whether the next process in the
queue is in memory.

If it is not, and if there is no free memory region, the dispatcher
swaps out a process currently in memory and swaps in the
desired process.
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Basic Memory
Management Methods
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Basic Memory Management schemes
Mem. Manegment schems
(/strategies)
Continuous Allocation
Multiple-partition
method
(Fixed-partition
allocation)
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Paging
Segmentation
variable
size
method
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Continuous Allocation
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Contiguous Memory Allocation (CMA)

The memory is usually divided into two partitions:


One for the resident OS
One for the user processes.

We can place the OS in either low memory or high memory .

Basic methodology:

Each process is contained in a single contiguous section of
memory.
 CMA strategy can be applied in (2) methods:


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Multiple-partition method/(Fixed-partition allocation) method
variable-partition allocation method
Dr. Abeer Mahmoud
Memory Allocation

Method #(1): Multiple-partition method (/Fixed-partition
method)

Main idea: divide memory into several fixed-sized partitions.
Each partition may contain exactly one process.

In this method:



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When a partition is free, a process is selected from the input queue and is
loaded into the free partition.
When the process terminates, the partition becomes available for another
process.
The degree of multiprogramming is bound by the number of partitions
Dr. Abeer Mahmoud
Memory Allocation (cont.)

Method #(2): variable-partition method:
o
o
o
o
o
o
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Memory is divided into variable-sized partitions
OS maintains a list of allocated / free partitions (holes)
When a process arrives, it is allocated memory from a hole
large enough to accommodate it
Memory is allocated to processes until requirements of next
process in queue cannot be met
OS may skip down the queue to allocate memory to a
smaller process that fits in available memory
When process exits, memory is returned to the set of holes
and merged with adjacent holes, if any
Dr. Abeer Mahmoud
Memory Allocation (cont.)
 Example:
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Memory Allocation (cont.)


New problem appear in variable-partition method…(how to
satisfy a request of size (n) from a list of free holes??? )
There are many solutions to this problem:
First fit.
Best fit
Allocate the first hole that
is big enough.
o Searching can start either
at the beginning of the set
of holes or where the
previous first-fit search
ended.
o We can stop searching as
soon as we find a free
hole that is large enough.
Allocate the smallest hole
that is big enough.
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We must search the entire
list, unless the list is
ordered by size.
This
Worst fit.
Allocate the largest hole.
we must search the entire list,
unless it is sorted by size.
This strategy produces the
largest leftover hole, which
may be more useful than the
smaller leftover hole from a
best-fit approach.
Dr. Abeer Mahmoud
Memory Allocation (cont.)

Exercise (8.16): Given five memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and
600 KB (in order), how would each of the first-fit, best-fit, and worst-fit algorithms place
processes of 212 KB, 417 KB, 112 KB, and 426 KB (in order)? Which algorithm makes
the most efficient use of memory?
>>> Let p1, p2, p3 & p4 are the names of the processes
First-fit:
Best-fit:
P1>>> 100, 500, 200, 300, 600
P1>>> 100, 500, 200, 300, 600
P2>>> 100, 500, 200, 88, 600
P2>>> 100, 288, 200, 300, 600
P3>>> 100, 83, 200, 88, 600
final set
P3>>> 100, 288, 200, 300, 183
of holes
P4>>> 100, 83, 88, 88, 600
100, 116, 200, 300, 183
100, 83, 88, 88, 174
P4 (426K) must wait
Worst-fit:
P1>>> 100, 500, 200, 300, 600
P2>>> 100, 500, 200, 300, 388
P3>>> 100, 83, 200, 300, 388
100, 83, 200, 300, 276 << final set of hole
P4 (426K) must wait
In this example, Best-fit turns out to be the best because there is no wait processes.
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Fragmentation


Fragmentation is a problem appears in memory allocation
censers about unusable memory space.
Fragmentation types:
External fragmentation
Internal Fragmentation
: memory space to satisfy a request : allocated memory may be larger
is available, but is not contiguous
than requested memory….
(i.e. storage is fragmented into a large
number of small holes)
(i.e. some memory within partition may
be left unused)
o Both the first-fit and best-fit strategies for
memory allocation suffer from external
fragmentation.
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Fragmentation (Cont.)
 External fragmentation solution:

Compaction: Memory contents shuffled to place all free
memory together in one large block (expensive)

Permit the logical address space of the processes to be noncontiguous, thus allowing a process to be allocated physical
memory wherever it is available.

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Two techniques achieve this solution:
Paging
Segmentation
Dr. Abeer Mahmoud
Fragmentation in
Continuous memory allocation scheme
fixed-partition method
suffer from internal
fragmentation
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variable-partition method
suffer from external
fragmentation
Dr. Abeer Mahmoud
Paging
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Paging

Paging is a memory-management scheme that permits the
physical address space of a process to be non-contiguous.

Because of its advantages, paging in its various forms is commonly
used in most OSs.
Recent designs have implemented paging by closely integrating the
hardware and OS, especially on 64-bit microprocessors.


Paging method also used to manage backing store (e.g. hard disk)
.
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Paging: Basic Method


The basic methodology:

Breaking physical memory into fixed-sized blocks called
frames

Breaking logical memory into blocks called pages… Where
(frame size= page size)
When a process is to be executed, its pages are loaded into
any available memory frames from the backing store.
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Paging: Basic Method

The backing store is divided into fixed-sized blocks that are
of the same size as the memory frames.

OS keeps track of free frames.
Page table translates logical page to physical frame addresses


Frame size:
 Defined by hardware
 Should be power of 2
 Usually between 512 byte- 16MB
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Paging: Basic Method (cont.)
Figure 8.8 Paging model of logical and physical memory.
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Paging: Basic Method (cont.)

Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table
which contains the corresponding frame number
 Page offset (d) – is the displacement within the page.
Where:
 m= number of bits in logical address
 n= number of bits in offset part
 m-n= number of bits in page number part
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Paging: Basic Method (cont.)

Example:
Given:
Page# 0
Frame #0
Page# 1
Frame #1
n=2 bits
m=4 bits
Page size=4 B
Page# 2
Frame #2
Page# 3
Frame #3
Physical mem. Size=32 B
# of pages= 8 pages
Convert the logical address (13)
to physical address.
Base address is the physical
address of first byte in
the target frame
How to convert from logical address to physical address in
paging???
Physical address = base address+ offset
= (frame # * frame size) + offset
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.
.
.
.
.
.
.
.
.
Frame #7
Dr. Abeer Mahmoud
Paging: Basic Method (cont.)

Example. (Cont.):
Physical address = base address+ offset
= (frame # * frame size) + offset
Logical address= 13 (in decimal) = (1101) in binary
Page # = (11) = 3
Offset= (01)= 1
By using the page table>>> frame # = 2
>>> Physical address of logical address (13) =(2* 4) + 1=9
Exercise: Convert the following logical addresses (given in decimal) to physical for
the same example: (0, 4,10,15)
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Paging Arithmetic Laws
 Page size = frame size
 Logical address space (/size) = 2m
 Physical address space (/size) = 2x (where x is the number of bits
in physical address)
 Logical address space (/size) = # of pages × page size
 Physical address space (/size) = # of frames × frame size
 Page size= frame size= 2n
 # of pages= 2m-n
 # of entries (records)in page table = # of pages
 Required number of pages for a process = process size/ page size
(Rounded up)
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Paging: Basic method(Cont.)
Frame allocation procedure:
 When a process arrives in the
system to be executed:

Process size ( expressed in pages) is
examined. …(i.e. if the process
requires (n) pages, at least (n) frames
must be available in memory)

If (n) frames are available then they
are allocated
when a page is loaded into a frame, its
frame number is put into the
page table for this process

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Figure 8.10 Free frames (a) before allocation and (b) after
allocation
Dr. Abeer Mahmoud
Paging: Basic Method (cont.)

Paging scheme has NO external fragmentation but it has an
internal fragmentation
Example:
If process (p1) size= 1030 B , page size= 512 B How many pages P1
will occupied??
 Required # of pages= 1030/512≈ 2.01 3 pages
 Notice that the last page is almost empty…. (506 bytes are
allocated and unused)……. (Internal fragmentation)….what is
the solution??
 Make page size small to reduce the internal fragmentation
Unsuitable solution because: (Page table size will
increased…(more memory consumption & moreover head)

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Paging hardware

The hardware implementation of the page table can be done in several ways.
Storing PT in
dedicated registers:
registers are
privileged
Acceptable solution if
page table is small
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Storing whole PT in RAM :
This method is used if PT is large
(common)
o Two physical memory
accesses are needed per user
memory access (one for the
page-table entry, one for the
byte).
memory access is slowed by
factor of 2>>> this delay is
unacceptable!!
Use a cash (TLB):
The search is fast but the
hardware is expensive.
TLB holds subset of page
table entries
Dr. Abeer Mahmoud
Paging hardware (cont.)

Hit ratio:
percentage of times
that a page # is
found in TLB

Effective
memory access
time :average time
for a memory
access (including
TLB lookup)
Figure 8.11 :Paging hardware with TLB.
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Paging Hardware (Cont.)

Example: IF [ TLB lookup: 20ns, Memory access time: 100ns, Hit
ratio: 80%]…Calculate the effective memory access time

If TLB hit
( it takes (1) TLB access & (1) memory access)
TLB hit = 20+ 100 = 120 ns

If TLB miss ( it takes (1) TLB access & (1) memory access
to read PT & (1) memory access to access the
desired byte )
Memory access time if TLB miss= 20+ 100 +100 = 220 ns
 Hit ratio =80% So, miss ratio= 20 %
Effective access time = (0.8 × 120) + (0.2 × 220) = 140ns
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Protection in Paging

Memory protection in a paged environment is accomplished by
protection bits associated with each frame. Normally, these bits
are kept in the page table.

One bit can define a page to be read-write or read-only.
 Every reference to memory goes through the page table to find
the correct frame number. At the same time that the physical
address is being computed, the protection bits is checked to
verify that no writes are being made to a read-only page.

An attempt to write to a read-only page causes a hardware trap
to the operating system
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Protection in Paging

One additional bit is generally attached to each entry in the
page table: a valid-invalid bit.
Bit== Valid
 the page is in the
process's logical address
space and is thus a legal (/
valid) page.
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Bit== Invalid
 the page is not in the
process's logical address
space.
 Illegal addresses are trapped by
use of the valid-invalid bit.
 The OS sets this bit for each
page to allow or disallow access
to the page.
Dr. Abeer Mahmoud
Protection in Paging (Cont.)

Example: Consider a system with a 14-bit
address space , we have a program that
should use only addresses 0 to 10468. the
page size is 2 KB. What are the valid pages
for this program??
m = 14 ,, page size =2 KB= 2 11 B
Logical address space = 2 m = 214 =16384 B
Logical addresses range (0- 16383)
# of required pages I for this program=
 Addresses in pages 0, 1, 2, 3, 4, and 5
program size / page size
are mapped normally through PT.
= 10469 / 2 11 = 5.11 ≈ 6 pages

Valid pages for this program: pages #
0,1,2,3,4,5.
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Any attempt to generate an address in
pages 6 or 7 the computer will trap
to the OS
Dr. Abeer Mahmoud
Shared Pages

An advantage of paging is the possibility of sharing common
code.This is particularly important in a time-sharing environment.

Example:
 Consider a system that supports 40 users, each of whom
executes a text editor



If the text editor consists of 150 KB of code and 50 KB of data
space we need 8,000 KB to support the 40 users .
If the code shared the required memory space =2,150 KB
Only one copy of the editor need be kept in RAM. Each user's page table maps
onto the same physical copy of the editor, but data pages are mapped onto
different frames.
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Shared Pages (Cont.)
Figure 8.13 : Sharing of code in a paging environment.
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Segmentation
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Segmentation

Users prefer to view memory as a collection
of variable-sized segments, with no
necessary ordering among segments.

Address space is made up of variablesized logical segments e.g. main
function, subroutines, some data
structures (list, array, stack, etc.), . . .

Segmentation is a memory-management scheme that supports
the user view of memory where a logical address space is a
collection of segments.
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Segmentation (cont.)

Each segment has a name and a length.

The addresses specify both the segment name and the offset
within the segment.


The user therefore specifies each address by two quantities:
1. a segment name ….(replaced by segment # for simplicity)
2. an offset
Logical addresses specify < segment identifier, offset >

Segmentation suffer from external fragmentation
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Segmentation: Hardware

Segment Table: used to convert from logical to physical addresses
 Segment table entry = ( segment base, segment limit )
 Base = starting physical address of segment in memory
 Limit = size of segment

Logical address consist of :
 Segment number (s) -- used as an index into a segment table .
 Segment offset (d)- is added to base address to define the
physical memory address
 The
offset of the logical address must be between 0 and the
segment limit. If it is not, we trap to the OS (logical
addressing attempt beyond end of segment).
.
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Segmentation: Hardware (Cont.)
How to convert from logical address to physical address in segmentation???
IF (offset < limit) then
Physical address= base address+ offset
Figure 8.19: Segmentation hardware
Else
Trap (address error)
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Segmentation: Hardware (Cont.)

Example: Consider the segmentation system shown in the figure. Convert
the following logical addresses (given in decimal) to physical addresses.
case(1):
L.A.= 2,53
Segment # =2
Offset= 53
Base= 4300
P.A. = 4300+53=4353
case(2):
L.A.= 0, 1222
Segment # = 0
Offset= 1222
Offset (1222) is not less than limit (1000) …
So, it is illegal reference, trap to operating
system
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Thank you
End of
Chapter 8
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