Transcript Some “facts” about software…

Where We’ve Been
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Binary representations
Boolean logic
Logic gates – combinational circuits
Flip-flops – sequential circuits
Complex gates – modules
Circuit design techniques
Assembly language programming
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What We Can Do
• Create digital systems
– Interconnection of modules to accomplish a
specific task
– Through an appropriate set of modules and
connections we can create a digital computer
– Rather than show the circuits in all their
glorious detail we use an abstract representation
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Architectural Functional Block
Diagram
ADDRESS BUS (External) 16 bit
Internal Memory
Internal data bus
Instruction
Reg ister
Ac c
B
Accumulator
I ns truc tion
dec oder/
c ontrol logic
Temporary
register
Temporary
register
PSW
flags
C ontrol Lines
C
AC
F0
RS1
RS2
OV
P
RD/ WR/ PSEN/
ALE/ etc.
ALU
8-bit
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DATA BUS (External) 8 bit
I-RAM
General Registers
STACK
Bit-addressable
SFRs etc.
P. C.
D PTR
Memory Addres s
R egist er
(Us es P0 and P2)
So What?
• A digital computer is a fascinating thing in and of
itself but somewhat useless
• It is the job of the programmer to make it do
something useful
• The programmer’s job is to supply specific,
detailed instructions to move and manipulate
binary data patterns within the architecture to
accomplish a meaningful task
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Sounds Easy
• The problem is that we [the programmers] don’t
want to be burdened with the knowledge of gates,
registers, flip-flops, etc.
• So, we describe the architecture in terms of
various parameters useful to the programmer
• Note that “the programmer” may not be an
“applications programmer” – it may be a
“language compiler writer”, for example
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Descriptive Parameters
• The set of registers within the architecture
– The names and functions (uses) of the registers
• The set of operations available for moving data
between registers and manipulating data contained
within registers
– Microoperations
• The method of specifying the sequence of
execution of the microoperations
• Note that this is a level lower than assembly
language
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Microoperations
• To describe the operations we use a
language called Register Transfer Language
• We [as programmers] assume that the logic
circuits [combinational and/or sequential]
are available to perform the “transfers”
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Register Transfer Language
• A register is nothing but a small, fast piece
of memory
• A system for expressing in symbolic form
the micro-operation sequences among the
registers of a digital module
• Note [again] that this is not Assembly
Language!!!
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Register Transfer Language
(RTL)
• Registers are designated by capital letters
–
–
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–
–
MAR – Memory Address Register
PC – Program Counter
IR – Instruction Register
Rx – General purpose register
etc.
• Bits within registers are numbered 0 to n-1 (n-bit
register) starting at the LSB (rightmost bit)
• What are registers made of?
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Register Representations
(Pictorial)
R1
7 6 5 4 3 2 1 0
7
0
R1
15
0
15
R2
8 7
R2(H)
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0
R2(L)
Register Transfers
• Move the data from one register to another
R2
R1
• The bit pattern that is in register R1 is copied into
register R2
– Again, we are assured that the circuitry required to
perform the transfer is available
– Implies a parallel load operation
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Conditional Transfer
• Conditionally move the data from one register to
another
if (P = 1) then R2
R1
• The bit pattern that is in register R1 is copied into
register R2 if the control signal P is high (1)
– This isn’t a Java “if/then” statement!
– Again, we are assured that the circuitry required to
perform the transfer is available
– Implies a parallel load operation
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Control Function
• Conditionally move the data from one
register to another
P: R2
R1
• Same meaning as the if/then statement
• P may be [typically is] a complex logic
expression/combinational circuit
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Hardware Implication
P: R2
Control
circuit
P
Load
R1
R2
clock
n
R1
• Rising edge of clock
sets the load signal
• Next rising edge cause
the transfer to occur
clock
load
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Parallel Operations
• Some microoperations take multiple clock cycles
(periods)
• Some microoperations can be performed
simultaneously (in parallel)
– During the same clock edge transition
P: R2
R1, R3
R0
– It’s this kind of operation that distinguishes between
computers and “super computers”
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Data Paths
• We’ve been assuming that the circuitry to
perform the transfers exists
• Two choices for realizing this assumption
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Data Paths
• Lots and lots of little wires
• Every register pair that can transfer data
must be wired together
C3 C2 C1 C0
B3
B2
B1
B0
A3 A2 A1 A0
3
3
2
1
0
3
2
1
0
register C
register B
2
1
0
register A
D3 D2 D1 D0
3
2
1
register D
0
• You would have to do this
for all registers!
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Data Paths
• Common bus
– A set of n wires (for n-bit register transfers)
shared by all registers
– Registers take turns putting their bit patterns
onto the bus
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Bus Implementation
bit 3
bit 2
bit 1
bit 0
select 1
select 0
4x1
MUX
3
2
1
D3 C3 B3
4x1
MUX
0
3
2
1
A3
D2 C2 B2
4x1
MUX
0
3
A2
2
1
4x1
MUX
0
3
2
1
D1 C1 B1
A1
D0 C0 B0
0
A0
D3 D2 D1 D0
C3 C2 C1 C0
B3
B2
B1
B0
A3 A2 A1 A0
3
3
3
2
1
0
3
2
1
register D
0
2
1
0
register C
register B
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2
1
register A
0
Bus Implementation
• Completing the transfer (we now have data
bits from a register on the bus)
– Simple – we just connect the bus data lines to
the inputs of the registers
– The data is then available to all registers on the
bus
– We activate the Load line for the actual
destination register
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Register Transfer Language
• In long-hand:
BUS
R1, R2
• In short-hand
R2
R1
• Bus activation is implied
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BUS
Three-State Gates
• In constructing the bus we used
multiplexers
– Convenient but expensive in terms of size and
money
• An alternative is the three-state gate
– Similar to the logic gates we’ve looked at so far
(NOT, AND, OR, NAND, NOR, XOR)
– Different in that they’re not binary
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Three-State Gates
• Three-state gates have a 3rd output value
that corresponds to “no output”
– When in this state the gate is effectively out of
the circuit – it acts as if it isn’t even there
– Technically, this is called a high-impedance
state and acts as an open circuit
• You’ll also here these called tri-state gates
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Three-State Gates
• The most common tri-state gate is the buffer
• What’s a buffer?
input output
• What’s a tri-state buffer?
input
output
control
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0
0
1
1
input
control
output
0
0
open
0
1
0
1
0
open
1
1
1
Tri-State Buffer Usage
from registers
bit 0
A0
B0
C0
D0
bus lines
from registers
Select
S1
S0
Enable
E
2x4
Decoder
0
1
2
3
A3
B3
bit 3
C3
D3
─ 1 decoder
─ A bunch of buffers
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Memory Transfers
• Recall we must specify a direction
(read/write), a source address, and a
destination address
• Read from memory location at address in
the AR register (Address Register) and
place the contents into the R1 register
Read: R1
M[AR]
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Memory Transfers
• Write (copy) the contents of register R1 to
the memory location at address in the AR
register (Address Register)
Write: M[AR]
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R1
Register Transfer Language (RTL)
Arithmetic Operations
Addition
R2 R1 + R3
Subtraction
R2 R1 - R3
Increment
R2 R1 + 1
Decrement
R2 R1 - 1
Complement (invert bits)
R2 R1
Negate (2’s complement)
R2 R1 + 1
R2 R2 + R1 + 1 Subtraction
• We need circuits to do all these operations
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Binary Adder Circuit
• Recall there are two
types of adder
S
– Half adder
• Adds two bits
• Produces a sum and carry
C
– Full adder
• Adds three bits
• Produces a sum and carry
S
C
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Creating Larger Adders
• Connect full adders together
– n-bit binary adder is created from n full adders
B3
A3
Full Adder
Cout
S3
B2
C3
A2
B1
Full Adder
C2
S2
A1
Full Adder
S1
4-bit binary adder
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B0
C1
A0
Full Adder
S0
C0
Binary Subtractor
• Subtraction is performed by a 2’s complement
operation followed by an addition
B3
Full Adder
Cout
S3
B2
A3
C3
B1
A2
Full Adder
C2
S2
Full Adder
S1
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B0
A1
C1
A0
Full Adder
S0
M
C0
Incrementer
• Can use a binary adder with a 1 as the 2nd input
• Can be done more simply with a series of half
adders
A3
A2
A1
A0
Half
Adder
Half
Adder
Half
Adder
Half
Adder
C3
S3
C2
S2
C1
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S1
C0
1
S0
Decrementer
• Subtractor with a 1 at the 2nd input
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Arithmetic Unit
• We don’t want all these separate circuits in
our system
– Too much space, too much complexity, too
much money
• Can we combine all these operations in a
single circuit?
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Arithmetic Unit
Cin
A0 S1S0
S0 S1
B0
0 1 2 3
4x1 MUX
A1
B1
S0 S1
A2
0 1 2 3
B2
S 0 S1
4x1 MUX
0 1 2 3
4x1 MUX
A3
S0 S1
0 1 2 3
4x1 MUX
Full Adder
Full Adder
Full Adder
Full Adder
D0
D1
D2
D3
Note: MSB is on the right, LSB is on the left
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0
B3
Cout
Select Lines Set To 00
Cin
A0 S1S0
S0 S1
B0
0 1 2 3
4x1 MUX
A1
B1
S0 S1
A2
0 1 2 3
4x1 MUX
Full Adder
Full Adder
D0
D1
B2
S 0 S1
0 1 2 3
4x1 MUX
Full Adder
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A3
0
B3
S0 S1
0 1 2 3
4x1 MUX
Full Adder
D3
Cout
Select Lines Set To 01
Cin
A0 S1S0
S0 S1
B0
0 1 2 3
4x1 MUX
A1
B1
S0 S1
A2
0 1 2 3
4x1 MUX
Full Adder
Full Adder
D0
D1
B2
S 0 S1
0 1 2 3
4x1 MUX
Full Adder
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A3
0
B3
S0 S1
0 1 2 3
4x1 MUX
Full Adder
D3
Cout
Select Lines Set To 10
Cin
A0 S1S0
S0 S1
B0
0 1 2 3
4x1 MUX
A1
B1
S0 S1
A2
0 1 2 3
4x1 MUX
Full Adder
Full Adder
D0
D1
B2
S 0 S1
0 1 2 3
4x1 MUX
Full Adder
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A3
0
B3
S0 S1
0 1 2 3
4x1 MUX
Full Adder
D3
Cout
Select Lines Set To 11
Cin
A0 S1S0
S0 S1
B0
0 1 2 3
4x1 MUX
A1
B1
S0 S1
A2
0 1 2 3
4x1 MUX
Full Adder
Full Adder
D0
D1
B2
S 0 S1
0 1 2 3
4x1 MUX
Full Adder
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A3
0
B3
S0 S1
0 1 2 3
4x1 MUX
Full Adder
D3
Cout
Summary
Select
S0
S1
Cin
1st Operand
2nd Operand
Output (D)
Microoperation
0
0
0
A
B
A+B
add
0
0
1
A
B
A+B+1
add with carry
0
1
0
A
B’
A + B’
subtract with borrow
0
1
1
A
B’
A + B’ + 1
subtract
1
0
0
A
0
A
transfer (assignment)
1
0
1
A
0
A+1
increment
1
1
0
A
1
A-1
decrement
1
1
1
A
1
A
transfer (assignment)
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Where are we?
• This takes us up to section 4-5
• Homework:
– 4-1, 4-2, 4-3, 4-6, 4-7, 4-8
– Due next lecture
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