Transcript Slide 1

I NV E N TIV E
CONFIDENTIAL
Is Co-existence Possible?
David White
Virtual Manufacturing Use Model
Prediction Step
Calibration Step
Fabricate
Test Wafer
(ECP/CMP)
Test Wafer
Design
Layout File
Data from ECD
& CMP
Processing
Measurement
Results
ECD/CMP
Virtual Mfg
Process Library
Data From
Test Wafer
Geometry
Extraction
Calibrate
Model
Product
Design
Layout
File
Geometry
Extraction
Predict
New Design
Full-Chip
Prediction
Semi-Physical
Model Tailored to
Specific Process
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July 18, 2015
ECD/CMP
Virtual Mfg
Process Library
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Tailored to
Customer’s
Process & Design
Topographical
Analysis
What Are Pattern-Process Interactions
Structures with Same Line widths, Same Local Density,
and Same Polish Conditions Have Very Different Cu Loss
Memory
Analog
IP Blocks
Rotated
IP Block
High
CPU
Block
Thickness
Low
IITC 2005, Nagaraj NS: “Copper and Low k
Scaling Challenges: A Design Perspective”
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July 18, 2015
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Accounting For Variation in Design Process
Actual Thickness
+20%
Systematic &
Random
Thickness
Manufacturing
Variation
Guardband
Systematic
Thickness
Manufacturing
Variation
Guardband
-20%
Current “2D” Methodology is Conservative Full Chip Guardband
for Both Systematic and Random Thickness Variation (+- 20%)
+10%
Actual Thickness
-10%
Random
Thickness
Manufacturing
Variation
Guardband
Cadence “3D” Methodology Eliminates Systematic Guardband
Leaving Only a Relatively Small Random Thickness Variation (+- 10%)
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July 18, 2015
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Experimental Results: CMP Aware Routing
Normalized Variation
CMP variation
1
0.98
0.96
0.94
0.92
0.9
0.88
0.86
0.84
• On average 7.5% reduction
• Up to 10.1% reduction
ibm01
ibm03
ibm05
BoxRouter
ibm07
ibm09
Wire density
Normalized timing
Timing
1
0.98
0.96
0.94
0.92
0.9
0.88
0.86
0.84
• On average 7% reduction
• Up to 10% reduction
ibm01
ibm03
BoxRouter
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July 18, 2015
ibm05
ibm07
Wire density
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ibm09
[Cho et al, ICCAD’06]
Rules versus Models as Function of
Pattern-Process Dependent Interaction
MORE
(Volumes)
Non-linear, multi-dimensional process or system
HIGH
Complexity
LESS
LOW
LOCAL
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July 18, 2015
Value of Models
Value of Rules
Complexity
Process Interaction
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GLOBAL
Deficiencies with Pure Rules Based Approach
Results in
Loss of
Accuracy
Characterization of
Pattern-Process
Behavior
Pattern
Geometries
Design
Rules
Little Value Back to
Manufacturing
Manufacturing
Customer
Capturing all
meaningful
interactions into rules
Violations &
Scoring Metrics
Local versus
global
interactions
Design
Customer
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July 18, 2015
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Design
Tools
Deficiencies with Pure Model Based Approach
Significant Value Back
to Manufacturing
Characterization of
Pattern-Process
Behavior
Speed?
Pattern
Geometries
Process
Models
Manufacturing
Customer
Volumes
of Data
(width and thickness
dimensions)
No Filtering
of Data
Design
Tools
e.g. 25M
thickness
values
Why does speed have question mark?
To be addressed later
Results in
Speed and
Data Issues
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July 18, 2015
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Design
Customer
What to
do with
Data?
How does
it impact
my
design?
Rules and Models Not Mutually Exclusive
Significant Value Back
to Manufacturing
Characterization of
Pattern-Process
Behavior
Manufacturing
Customer
Global Pattern
Geometries
Speed
Volumes
of Data
Process
Models
Local Pattern
Geometries
Accuracy
(width and thickness
dimensions)
Design
Rules
Violations &
Scoring Metrics
Design
Customer
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July 18, 2015
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Design
Tools
65nm Rule Deck Example
• Ran three separate 65nm rule decks on 65nm production design
• 96% of operation counts are done with 0 halo size
• Density rules using 100 micron window size are less than 1% of
overall operations but 5% of overall execution time
100%
90%
80%
100%
70%
90%
60%
50%
80%
% Operation Counts
70%
% Execution Time
40%
60%
30%
50%
20%
40%
% Operation C
% Execution Ti
30%
10%
20%
0%
Halo Size
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dw
sz
3
28
28 113
.3 .2
1
56 41.5
.6 1
69
.8
84
.9 198
.1
11
2
3. 26
2 .4
14 25
1. 4.7
5
28
16
3
9.
d
8 w
sz
19
8.
1
22
6.
4
25
4.
7
0 84.9
.6
0%
56
.3
28
0
10%
Backup / Q&A
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Models Complement Rules
Design Rules Say OK, Models Say Its Not Acceptable
Metal 4 Copper Density
Metal 4 Copper Loss
0.70  1200A
0.70  2500A
•
•
Both Areas Have 70% Average
Density
But Very Different Copper Loss
1200A
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July 18, 2015
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2500A
Process for Forming Interconnect (Wires)
Features Defined Through
Lithography and Etch
dielectric
copper
ECD Copper Plating
Step 1: Copper Plating
dielectric
Copper CMP (Bulk)
Step 2: Bulk Polish
Copper CMP (Touchdown)
Step 3: Copper Clear or Touchdown
Copper CMP (Barrier)
Step 4: Barrier Removal
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July 18, 2015
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Rules versus Models as Function of
Uncertainty in Process Characterization
MORE
(Volumes)
Non-linear, multi-dimensional process or system
HIGH
Value of Models
Value of Rules
LESS
LOW
POORLY
CHARACTERIZED
UNSTABLE PROCESS
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July 18, 2015
Process Maturity
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WELL
CHARACTERIZED
STABLE PROCESS
Chemical Mechanical Polishing
Force
Modern polishing
heads have separate
rings where the force
can be radially
adjusted
Table with Pad Rotating
Within-Chip Variation: dominated by layout, pad and slurry interaction
Within-Wafer Variation: dominated by pressure zone apportionment in
carrier and relative velocities of carrier and table
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July 18, 2015
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Interconnect Variation
Wafer Level
Variation
•
•
•
Within-Chip Variation is Huge!
– Thickness Variation: 10% to 30%
– Width Variation: 10% to 30%
Due to Design Impact on Manufacturing
– Varying Feature Density
– Varying Feature Widths
Variation Leads to Over-Compensation in Design
– Timing Failures
– Decreased Performance
– Increased Power Consumption
Within-Chip
Variation
Oxide Loss
Dishing
Isolated
Isolated
Thin-Lines Wide-Lines
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July 18, 2015
Total Copper Loss
Dense Array
Thin-Lines
Dense Array
Wide-Lines
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Wafer
Surface
Chip
Surface
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July 18, 2015
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