Transcript Presentation kit

A Reconfigurable Design-for-Debug
Infrastructure for SoCs
Miron Abramovici
Peter Levin
Paul Bradley
Gerard Memmi
Kumar Dwarakanath
Dave Miller
Silicon Debug: Growing Barrier to Market Entry
Spec
180nm
$4.2M
~12 mo
RTL
Netlist
1st Si
Debug &
Qualification
~ 17% of
TTM
130nm
$10.8M
~15 mo
> 28% of
TTM !
90nm
$25.8M
~18 mo
> 35% of
TTM ?
Traditional Debug Strategies Failing
Source: Collett ASIC/IC Verification Study 2004 (180nm / 130nm)
Post-Silicon Debug Problem Statement
 1st Silicon often doesn’t work
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
More than 50% of new chips have functional issues
After substantial and expensive pre-silicon verification
 Post-silicon debug is expensive


Average debug and validation period (at 90nm): 6 months
Economic impact of delayed ramp to production: $ tens
of millions
 Post-silicon debug is challenging


Very limited observability of chip-internal signals
On-chip clock frequency often too high for external
access
In-System At-Speed Silicon Debug
 Required to validate silicon
 Exercises functionality and timing not
verified pre-silicon
Application program
 More constrained than tester-based
debug
 Expected values not known
 The problem may be caused by a
defect
 Problem difficult to reproduce on tester
 State-of-the-art

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
Ad-hoc debug structures
Time-consuming manual effort
Few commercially available tools
SoC Under Debug
A New Approach
 Distributed reconfigurable infrastructure fabric

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User-guided insertion compatible with existing design
flows
Soft IP inserted at RTL
Configured post-silicon for maximum debug flexibility
 Effective debug and verification platform
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Signal capture and analysis
Assertion-based debug
Stimulate and capture
What-if analysis
Event- and transaction-driven debug support
Design Flow Integration
Insert
Instrumentation
Synthesis
Physical Design
Customer Design
Debug
Environment
Prototype
Silicon

Accelerated
Debug &
Validation
Debug Structures
 Configured dynamically (when needed):
 triggers to start/stop recording of signals
 assertion checkers
 event detectors
 event counters
 pattern generators
 value injectors
…
…
 Configuration and instrument control via JTAG TAP
Instrumented Chip Example
 Signal Probe
Network
(transport/selection)
 DEbug MONitor
(analysis)
 Tracer
(capture)
 Wrapper
(analysis & control)
 CapStim
(capture/stimulate)
 JTAG
 Primary CONtroller
(instrumentation
access & control)
Tapping / Wrapping of Signals
Net_a
BEFORE
TAP
WRAP
Net_a
AFTER
MUX
Net_a
Delay: none
Load: 1 Gate
TAP: þ
WRAP: ¨
OBS: þ
SCTL: ¨
ASCTL: ¨
MOD: ¨
Wrap
Element
MUX
<X>_Net_a
Delay: 1 MUX
Load: 1 Gate
TAP: þ
WRAP: þ
OBS: þ
SCTL: þ
ASCTL: þ
MOD: þ
Supported Debug Paradigms
 Signal capture and logic analysis
 Assertion-based debug
 Stimulate and capture (in-situ, at-speed IP verification)
 Event- and transaction-driven debug
 Scan-based debug
 What-if analysis
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Fault/error injection
Soft fixes or ECOs
May be intermixed
Signal Probe Network (SPN)
Pipeline register
for enhanced
speed
FIFO
for clock domain
crossing
Daisy chain
for ease-of
routing
Aligner
for data path
balancing
Logic Analysis and Signal Capture
 DEMON block
implements triggers
 Signals captured by
Tracer
 Software reads trace
buffer and prepares
VCD or FSDB files
Monitors
Reconfigurable Monitor
 more flexible
Programmable Trigger Engine
 less area
 higher speed
CAPSTIM Instrument
 Used for in-situ IP verification
Assertion-Based Silicon Debug
 Assertions
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Properties that must be true in a correct circuit
Extensively used in pre-silicon verification
 Benefits
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Automatic continuous checks
Significant reduction in search space for root-cause
 Implement assertions in silicon
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Configure instrumentation with assertions
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User-defined assertions
Library of pre-set assertions
 Benefits

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Automatic continuous checks
Significant reduction in search space for root-cause
Implementing Assertions
 Use DEMONs and
wrappers
 Assertions run at
speed
 Concurrent assertions
 Large number of
assertions can be run
by reusing the fabric
for different groups
 No need for expected
values
 Help identifying
transient or deep-state
functional issues
Configuring Assertions
 Personality Editor
 Pre-set library

50+ assert functions
 Verilog compiler
What Signals To Instrument
 Tap signals identifying important transactions
 Identify high-risk areas
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new IP cores
new user-defined logic
logic with poor verification coverage
logic for new or evolving standards
 Tap signals likely to expose errors
(signals of interconnected high-risk FSMs)
 Tap input signals for assertions in high-risk areas
 Wrap signals likely to be modified
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for what-if experiments
for soft-fixes or ECOs
for fault/error injection
Infrastructure Investment
Tapped
Signals
1,024
4,096
8,192
Wrapped
Signals
PTE
Tracer
SPN
Wrap
102
409
819
1.16%
1.16%
1.16%
0.16%
0.16%
0.16%
0.11%
0.37%
0.74%
0.96%
3.84%
7.68%
Example:
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5M user gates
10% ratio tapped/wrapped
32bit debug bus
PTE with 16 states / 4
branches
Observability:
 8192 signals tapped
  2.1% additional gates
Observability & Control
 819 signals wrapped
  7.7% additional gates
Conclusions
 A new approach to silicon debug
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Reconfigurable debug infrastructure
On-chip observability and control
Support for many different debug paradigms
 Advantages

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Enables in-system at-speed debug and validation
Repeatedly configured for different debug structures
Accelerates debug in the lab and in the field
Eliminates the need for multiple respins
 Other applications
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Performance measurements
On-line testing
…
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