Transcript Basic Logic Gates

ROM
Lecture D7.5
ROM
addr(2:0)
0
1
2
3
4
5
6
7
85
C4
E6
55
67
D4
F4
C6
M(7:0)
ROM.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ROM is
port (
addr: in STD_LOGIC_VECTOR (2 downto 0);
M: out STD_LOGIC_VECTOR (7 downto 0)
);
end ROM;
addr(2:0)
0
1
2
3
4
5
6
7
85
C4
E6
55
67
D4
F4
C6
M(7:0)
architecture ROM_arch of ROM is
constant data0: STD_LOGIC_VECTOR
constant data1: STD_LOGIC_VECTOR
constant data2: STD_LOGIC_VECTOR
constant data3: STD_LOGIC_VECTOR
constant data4: STD_LOGIC_VECTOR
constant data5: STD_LOGIC_VECTOR
constant data6: STD_LOGIC_VECTOR
constant data7: STD_LOGIC_VECTOR
(7
(7
(7
(7
(7
(7
(7
(7
downto
downto
downto
downto
downto
downto
downto
downto
0)
0)
0)
0)
0)
0)
0)
0)
:=
:=
:=
:=
:=
:=
:=
:=
"10000101";
"11000100";
X"E6";
X"55";
X"67";
X"D4";
"11110100";
"11000110";
type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (7 downto 0);
constant rom: rom_array := (
data0, data1, data2, data3,
data4, data5, data6, data7
);
begin
0
85
process(addr)
1
variable j: integer;
C4
begin
2
E6
j := conv_integer(addr);
3
55
M <= rom(j);
addr(2:0)
M(7:0)
4
67
end process;
5
D4
end ROM_arch;
6
7
F4
C6