Transcript Lecture 10 Memory Design - Northwestern University

Lecture 11
Memory Design
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 11
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Outline
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Random Access Memories (RAMS)
Static RAMs
Dynamic RAMS
Memory Organizations
Read-Only Memories (ROMS)
READING: Katz 7.6, 4.2.5
ECE C03 Lecture 11
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Memory
• Need method for storing large amounts of data
– Computer programs, data, pictures, etc.
Address
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
Data
00111110
01101011
01011101
01100011
00111110
00000000
11111111
01010101
10101010
00100001
11011010
64x8 RAM
A3
A2
A1
A0
Write
D7
D6
D5
D4
D3
D2
D1
D0
• RAM: Random Access Memory, Read/Write
• ROM: Read-only Memory
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8x4 RAM
Address
Data
000
001
010
011
100
101
110
111
A2
A1
A0
ECE C03 Lecture 11
Out3
Out2
4
Out1
Out0
8x4 RAM
In3
Write
In2
In1
In0
000
001
010
3:8 011
Decoder
100
101
Enable
110
111
S2 S1 S0
A2
A1
A0
ECE C03 Lecture 11
Out3
Out2
5
Out1
Out0
RAM Cell
• Requirements:
– Store one bit of data
– Change data based on input when row is selected
Input
S
Q
Row Select
R
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Static Random Access Memories
Transistor efficient methods for implementing storage elements
Small RAM: 256 words by 4-bit
Large RAM: 4 million words by 1-bit
We will discuss a 1024 x 4 organization
Data
Word Enable
Data j
j
i
Words = Rows
Static RAM Cell
Static RAM Cell
Static RAM Cell
Columns
= Bits
(Double
Rail Encoded)
ECE C03
Lecture
11
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Static RAM Organization
Chip Select Line (active lo)
Write Enable Line (active lo)
10 Address Lines
4 Bidirectional Data Lines
ECE C03 Lecture 11
1024 x 4 SRAM
CS
WE
A9
A8
A7
IO3
A6
IO2
A5
IO1
A4
IO0
A3
A2
A1
A0
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RAM Organization
Long thin layouts are not the best organization for a RAM
A9
A8
Some Addr
bits select
row
Address
Buffers
Storage
Storage Matrix
Array
64 x 64
Square
Array
A7
A6
64 x 16
A5
A4
A3
Some Addr
bits select
within row
A2
64 x 16
64 x 16
64 x 16
Row
Decoders
Address
Buffers
Amplifers &
Mux/Demux
Sense Amplifiers
A1
A0
CS
WE
Column
Decoders
Data Buffers
I/O0 C03 Lecture
I/O1 11
ECE
I/O2
I/O3
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RAM Timing
WE
CS
Simplified Read Timing
Address
Valid Address
Acc es s Time
Data Out
Data Out
WE
CS
Simplified Write Timing
Memory Cycle T ime
Address
Valid Address
Data In
Input Data
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Dynamic Random Access Memories
1 Transistor (+ capacitor) memory element
Word Line
Read: Assert Word Line, Sense Bit Line
Write: Drive Bit Line, Assert Word Line
Destructive Read-Out
Need for Refresh Cycles: storage decay in ms
Bit Line
Internal circuits read word and write back
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DRAM Organization
Long rows to simplify refresh
Two new signals: RAS, CAS
Row Address Strobe
Storage Matrix
Row
Decoders
64 x 64
Column Address Strobe
replace Chip Select
Row Address
Column Address &
Control Signals
A11
. . .
A0
RAS
CAS
WE
Column Latches,
Multiplexers/Demultiplexers
Control
Logic
DOUT
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DIN
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RAM Addressing
Even to read 1 bit, an entire 64-bit row is read!
Separate addressing into two cycles: Row Address, Column Address
Saves on package pins, speeds RAM access for sequential bits!
Address
Row Address
Col Address
RAS
Read Cycle
CAS
Valid
Dout
Read Row
Row Address Latched
Read Bit Within Row
Column Address Latched
ECE C03 Lecture 11
Tri-state
Outputs
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RAM Write Timing
Address
Row Address
Col Address
RAS
(1) Latch Row Address
Read Row
CAS
WE
(2) WE low
Din
Valid
(3) CAS low: replace data bit
(4) RAS high: write back the modified row
(5) CAS high to complete the memory cycle
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DRAM Refresh
Refresh Frequency:
4096 word RAM -- refresh each word once every 4 ms
Assume 120ns memory access cycle
This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!
But RAM is really organized into 64 rows
This is one refresh cycle every 62.5 µs (1 in 500 DRAM accesses)
Large capacity DRAMs have 256 rows, refresh once every 16 µs
RAS-only Refresh (RAS cycling, no CAS cycling)
External controller remembers last refreshed row
Some memory chips maintain refresh row pointer
CAS before RAS refresh: if CAS goes low before RAS, then refresh
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Variations of DRAMs
Page Mode DRAM:
read/write bit within last accessed row without RAS cycle
RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...
New column address for each CAS cycle
Static Column DRAM:
like page mode, except address bit changes signal new cycles
rather than CAS cycling
on writes, deselect chip or CAS while address lines are changing
Nibble Mode DRAM:
like page mode, except that CAS cycling implies next column
address in sequence -- no need to specify column address after
first CAS
Works for 4 bits at a time (hence "nibble")
RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .
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RAM Expansion
• Implement a big RAM from multiple small RAMS
Address
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0000000
0010000
0100000
0110000
1000000
1010000
1100000
1110000
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RAM Expansion (cont)
• Build a 16x16 RAM from 16x4 RAMs
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
ECE C03 Lecture 11
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
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RAM Expansion (cont)
• Build a 32x16 RAM from 16x4 RAMs
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
16x4 RAM
A3
Din
A2
A1
Dout
A0
Write
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Read-Only Memories
This is another class of memory, which is read only, cannot write.
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
Dec
i
Word Line 0011
j
Word Line 1010
0
0
n-1
Address
Bit Lines
C03 Lecture 11
InternalECE
Organization
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ROMs vs PLAs
Memory array
Not unlike a PLA
structure with a
fully decoded
AND array!
Dec oder
2n word
li nes
n address
li nes
2n words by
m bits
m output
li nes
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
ECE C03 Lecture
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PAL problem: constrained fan-ins
on OR
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2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10 O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
Read-Only Memories
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
+
A13
/OE
A12:A0
D15:D8
D7:D0
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
+
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
16K x 16
Subsystem
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Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
Address
ROM
8 words ¥by
4 bi ts
A B C
addres s
F0
F1
F2
outputs
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
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Summary
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Random Access Memories (RAMS)
Static RAMs
Dynamic RAMS
Memory Organizations
Read-Only Memories (ROMS)
NEXT LECTURE: Finite State Machine Design
READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2
ECE C03 Lecture 11
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