Transcript A New Kind of Algebra

Gates – Part 1
ECEn 224
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Gates are Built With Transistors
drain
drain
3 volts
gate
source
nFET
drain
current
flows
no
current
flows
0 volts
source
source
nFET On
nFET Off
N-type field-effect transistor = nFet
ECEn 224
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Gates are Built With Transistors
source
source
0 volts
gate
drain
pFET
source
current
flows
no
current
flows
3 volts
drain
drain
pFET On
pFET Off
P-type field-effect transistor = pFet
ECEn 224
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Complement
Also known as invert or not.
x
0
1
x’
x
x'
1
0
This is a schematic symbol.
It is a graphical representation
of a circuit which implements
the operation.
ECEn 224
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FET-Based Inverter
Vcc = 3V
Vin
Vout
Vcc = 3V
Vcc = 3V
off
on
3V
0V
0V
3V
on
GND = 0V
GND = 0V
off
GND = 0V
“Ground”
ECEn 224
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AND and OR Gates
A
A
Q
Q
B
B
A B Q=A•B
A B Q=A+B
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
1
ECEn 224
0
1
0
1
0
1
1
1
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Boolean Expressions and Gates
Each Boolean expression has a corresponding realization
with logic gates.
F = A’ + B C
A
F
B
C
ECEn 224
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NAND Gates
AND
NAND
A
Q
A B Q=(A•B)'
0
0
1
1
0
1
0
1
B
1
1
1
0
Q is true iff A AND B are true
Bubble means NOT
NAND
A
Q
A
B
Q
B
Q is false iff A AND B are true
ECEn 224
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FET-Based NAND Gate
Vcc
A
Vcc
B
1
off 1
Vcc
1
off
F
off 0
on
0
1
A
1
on
1
on
B
1
on
0
off
GND
GND
ECEn 224
GND
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NOR Gates
OR
NOR
A
A B Q=(A+B)'
0
0
1
1
A
0
1
0
1
Q
B
1
0
0
0
Q is true if A OR B is true
NOR
Q
B
A
Q
B
Q is false if A OR B is true
ECEn 224
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FET-Based NOR Gate
Vcc = 5V
A
B
F
A
B
GND
A
B
F
0V
0V
5V
5V
0V
5V
0V
5V
?
?
?
?
Can you complete the truth table?
ECEn 224
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FET-Based NOR Gate
Vcc = 5V
A
B
F
A
B
GND
A
B
F
0V
0V
5V
5V
0V
5V
0V
5V
5V
0V
0V
0V
Can you complete the truth table?
ECEn 224
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FET-Based Gates
• P-type FETs must be on top of gate
• N-type FETs must be on bottom of gate
• Due to electrical characteristics of the two
FET types
• Output is driven to either ‘1’ or ‘0’
– never both
– never neither
ECEn 224
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Exclusive-OR (XOR)
Output is true iff inputs are different.
A B Q=AB
0
0
1
1
0
1
0
1
0
1
1
0
A
Q = A  B = A’B + AB’
B
Another definition: Q is true iff A does not equal B
ECEn 224
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Exclusive-OR Theorems
X0=X
X  1 = X'
XX=0
X  X' = 1
XY=YX
Commutative law
( X  Y)  Z = X  ( Y  Z ) = X  Y  Z
Associative law
( X  Y)' = X  Y' = X'  Y
The first 4 are important,
the others are used less frequently
ECEn 224
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Equivalence Operation
 denotes equivalence (also written as X==Y)
Output is true iff inputs are equal
X Y X==Y
0
0
1
1
0
1
0
1
1
0
0
1
X

Q = (X==Y)
= X’Y’ + XY
Y
ECEn 224
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XOR and EQUIV are Complements !!
X Y XY X==Y
Alternate equivalence
symbol
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
Gate often called exclusive NOR or XNOR
ECEn 224
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Multi-Input Gates
Vcc
A
B
Vcc
C
A
B
F
F
A
A

B

B
C
GND
GND
Which one will be slower/faster?
ECEn 224
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Alternative Gate Symbols
The symbolic meaning of the circuit
should be clear from what you draw...
ECEn 224
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Alternative Gate Symbols
A
Q
B
Q is true iff A is false OR B is false
A
B
Q
0
0
1
1
0
1
0
1
1
1
1
0
A
B
Q
0
0
1
1
0
1
0
1
1
0
0
0
A
Q
B
A
Q
B
Q is true iff A is false AND B is false
ECEn 224
A
Q
B
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Alternative Gate Symbols
• Turn on sprinklers if it is not a holiday and it
is not a weekend
or?
The problem statement uses AND,
so use the AND symbol
ECEn 224
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Alternative Gate Symbols
• Turn off the sprinklers if it is a holiday or it
is a weekend
or?
The problem statement uses OR,
so use the OR symbol
ECEn 224
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Another Example
• Design a circuit to determine whether the
bits of a 4-bit wire are all zero
This is the appropriate symbol to use…
ECEn 224
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Mixed Symbols
A
Q
B
Q is true iff A is false AND B is true
• Such a gate doesn’t likely exist
• Build from AND gate and inverter
• Simplifies schematics, enhances readability
ECEn 224
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Single Gate Conversion Rules
• How to change one symbol to another:
– Change symbol
• AND to OR
• OR to AND
– Invert all inputs and outputs
• No change in behavior – merely a symbol change
A
A
Q
Q
B
B
Q is true iff A is false AND B is true
ECEn 224
Q is false if A is true OR B is false
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Alternative Gate Symbols - Summary
• Use the symbol that matches the problem
statement
– Clarity
– Documentation
– Maintenance
• If function is correct but symbol is wrong
then your schematic is wrong
ECEn 224
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Positive vs. Negative Logic
ECEn 224
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Positive Logic and Negative Logic
V1
V2
V3
Logic
Gate
Vout
ECEn 224
V1
V2
V3 Vout
0V
0V
0V
0V
5V
5V
5V
5V
0V
0V
5V
5V
0V
0V
5V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
0V
0V
0V
0V
0V
0V
5V
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Positive Logic
Let:
0 volts => 0
5 volts => 1
V1
V2
V3 Vout
v1
v2
v3
vout
0V
0V
0V
0V
5V
5V
5V
5V
0V
0V
5V
5V
0V
0V
5V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0V
0V
0V
0V
0V
0V
0V
5V
The circuit is a logical AND gate
ECEn 224
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Negative Logic
Let:
0 volts => 1
5 volts => 0
V1
V2
V3 Vout
v1
v2
v3
vout
0V
0V
0V
0V
5V
5V
5V
5V
0V
0V
5V
5V
0V
0V
5V
5V
0V
5V
0V
5V
0V
5V
0V
5V
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0V
0V
0V
0V
0V
0V
0V
5V
The same circuit is a logical OR gate
ECEn 224
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Positive/Negative Logic
• The most common mapping is positive logic:
+V  1
0V  0
• Different systems have used different
mappings in the past
ECEn 224
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Multi-Level Logic
ECEn 224
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Levels of a Network
Maximum number of gates between an input
and the output
5 Levels
In general:
3 Levels
- the more levels,
the slower the circuit
ECEn 224
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Number of Levels
• Number of levels can be increased by factoring
G = AB + ACDE + ACF = A(B+CDE+CF)
• Number of levels can be decreased by multiplying out
G = A(B+CDE+CF) = AB + ACDE + ACF
• Changing the number of levels affects area and speed
ECEn 224
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Example
Levels = 2
Gates = 4
Delay = tAND4 + tOR3
Gate Inputs = 12
Transistors = 24
Largest gate = 4 inputs
G = AB + ACDE + ACF
A
B
A
C
D
E
A
C
F
G
Area Calculations:
- Each input to a gate costs ~2 transistors
- Area  number of transistors
Delay Calculations:
- Find slowest path from inputs to output
tdelay = tAND4 + tOR3
- The 4-input AND is likely slower than the
other AND gates
ECEn 224
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Change the number of levels by factoring
G = ACDE + ACF + AB = A(CDE + CF + B)
factor
C
D
E
C
G
F
B
A
Levels = 3
Gates = 4
Delay = tAND3 + tOR3 + tAND2
Inputs = 10
Transistors = 20
Largest gate = 3 inputs
This is a 3-level circuit…
ECEn 224
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Factor Again
G = A(CDE + CF + B) = A[B+C(F+DE)]
factor
A
D
C
B
G
E
F
Levels = 5
Gates = 5
Delay = 3 x tAND2 + 2 x tOR2
Inputs = 10
Transistors = 20
Largest gate = 2 inputs
This is a 5-level circuit…
ECEn 224
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Changing the number of levels
Three alternative solutions for same function…
2-level
3-level
5-level
Logic Levels
2
3
5
Delay tAND4 + tOR3 tAND3 + tOR3 + tAND2 3 x tAND2 + 2 x tOR2
Gate Count
4
4
5
Gate Inputs
12
10
10
Transistors
24
20
20
Largest Gate
4
3
2
Each has different area/speed characteristics
ECEn 224
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Two-Level vs. Multi-Level
• In general:
– Two-level is fastest
– Multi-level can be smaller
• Exploring by hand to find just the right solution can
be difficult
• We will focus on two-level
– Easy to get from truth table
– Minimization techniques in later chapters focus on it
ECEn 224
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