Transcript 投影片 1

VLSI Testing
積體電路測試
Introduction to Verilog HDL
Ping-Liang Lai (賴秉樑)
Department of Electronic Engineering, Notional Chin-Yi University of Technology
Outline




Introduction
Modules and Instance
Design Block and Stimulus Block
Four Levels of Abstraction




Gate-Level Modeling
Dataflow Modeling
Behavioral Modeling
Switch-Level Modeling
 Lexical Conventions
P.L.Lai, VLSI Testing 2009
Appendix 1-2
Introduction
 Hardware description language
 Mixed level modeling
 Single language for design and simulation
 Built-in primitives, logic function
 User-defined primitives
 Built-in data types
 High-level programming constructs
P.L.Lai, VLSI Testing 2009
Appendix 1-3
Modules
 A module can be an element or a collection of lower-level
design block
Syntax:
module <module_name> (<module_terminal_list>)
…
<module internals>
…
endmodule
Example:
module T_FF (q, clk, reset);
…
<functionality of T-flipflop>
…
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-4
Instances
// Define the top-level module called ripple carry counter. It
// instantiates 4 T-flipflops.
module ripple_carry_counter (q, clk, reset)
output [3:0] q;
// I/O signals and vector declarations
input clk, reset;
// I/O signals
T_FF tff0 (q[0], clk, reset);
T_FF tff1 (q[1], q[0], reset);
T_FF tff3 (q[2], q[1], reset);
T_FF tff4 (q[3], q[2], reset);
endmodule
module T_FF (q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0 (q, d, clk, reset);
// Instantiate D_FF. Call it dff0.
not n1 (d, q);
// not gate is a Verilog primitive.
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-5
4-bit Ripple Carry Counter
Ripple Carry Counter
q0
q1
q
clock
q2
q
T_FF
q3
q
q
T_FF
T_FF
T_FF
reset
q
T_FF
reset
ck
qn
qn+1
1
*
1
0
1
*
0
0
0
↓
0
1
0
↓
1
0
d
clock
q
D_FF
reset
P.L.Lai, VLSI Testing 2009
Appendix 1-6
Design Block and Stimulus Block
 Two styles of stimulus application


Stimulus block instantiates design block
Dummy top-level module
(Stimulus block)
clk
reset
Top-Level Block
d_clk
d_reset
Design Block
c_q
q
Fig. 1. Stimulus block
instantiates design block
P.L.Lai, VLSI Testing 2009
Stimulus Block
clk
reset
q
Design Block
Fig. 2. Stimulus and design blocks
instantiated in a Dummy top-level module
Appendix 1-7
Design Block
Ripple Carry Counter Top Block
module ripple_carry_counter (q, clk, reset);
output [3:0] q;
input clk, reset;
T_FF tff0 (q[0], clk, reset);
T_FF tff1 (q[1], q[0], reset);
T_FF tff3 (q[2], q[1], reset);
T_FF tff4 (q[3], q[2], reset);
endmodule
Flip-flop T_FF
Flip-flop D_FF
module D_FF (q, d, clk, reset);
output q;
input d;
input clk;
input reset;
reg q;
always @ (posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
module T_FF (q, clk, reset);
Example:
output q;
input clk, reset;
wire d;
D_FF dff0 (q, d, clk, reset);
not n1 (d, q);
endmodule
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-8
Stimulus Block
module rcc_testbench;
reg clk;
reg reset;
wire [3:0] q;
ripple_carry_counter r1 (q, clk, reset);
initial
always
initial
begin
end
initial
clk = 1'b0;
#5 clk = ~clk;
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish;
$monitor($time, "Output q = %d", q);
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-9
Four Levels of Abstraction
 Behavioral level

只考慮模組中的功能和函數，不必考慮硬體的特性，如同是在寫
C語言一樣
 Dataflow level

說明資料如何在暫存器中儲存和傳送，和資料處理的方式
 Gate level

模組是由Logic gates所構成的，使用Logic gates來設計電路
 Switch level

最低層次，設計者需知道電晶體的元件特性
P.L.Lai, VLSI Testing 2009
Appendix 1-10
Gate level
P.L.Lai, VLSI Testing 2009
Appendix 1-11
Behavioral
module Beh_AND ( in1 , in2 , Out)
input in1 , in2 ;
output Out ;
reg Out ;
always @ ( in1 or in2 )
begin Out = in1 & in2
end
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-12
Data Flow
module DF_AND ( in1 , in2 , Out)
input in1, in2 ;
output Out ;
wrie Out ;
assign Out = in1 & in2 ;
endmodule
P.L.Lai, VLSI Testing 2009
Appendix 1-13
四種準位數值
 0
 1
 X : 不確定
 Z : 高阻抗
P.L.Lai, VLSI Testing 2009
Appendix 1-14
Operators (1/3)
 Binary Operator





~
&
|
^
~^
NOT
AND
OR
XOR
XNOR
 Example

a= ~ b ;
»

// not
If b= 4’b0010, then a= 4’b1101
a= b & c; // and
»
If b= 4’b0011, c=4’b1010, then a= 4’b0010
P.L.Lai, VLSI Testing 2009
Appendix 1-15
Operators (2/3)
 Example

a= b | c;
»

// or
If b= 4’b0011, c= 4’b1010, then a= 4’b1011
a= b ^ c; // and
»
If b= 4’b0011, c= 4’b1010, then a= 4’b1001
P.L.Lai, VLSI Testing 2009
Appendix 1-16
Operators (3/3)
 Unary operator

a=~b;
 Ternary operator

a=b ? c : d;
P.L.Lai, VLSI Testing 2009
Appendix 1-17
常用敘述
 assign


驅動某個值到 wire , wand , wor ,tri
用於資料處理模型 Data Flow Model
wire a ,b, c;
// 宣告三個接線型態的變數
assign a= b & c; // a = b and c
 Always

可隨時監督外界輸出入port ,訊號有變化時即告訴模組內部配合相對應的
工作
always @(a or b)
begin
f=a&b&c;
end
P.L.Lai, VLSI Testing 2009
Appendix 1-18
常用敘述
 always example
// posedge 正緣觸發
always @ (posedge clock)
begin
…
end
// negedge 負緣觸發
always @ (negedge clock)
begin
…
end
P.L.Lai, VLSI Testing 2009
Appendix 1-19
常用敘述
 wire



接線是連接硬體元件之連接線
接線必須被驅動才能改變它內函值
內定為一個位元值 z
 reg



暫存器
功能與變數很像 ,可以給定一個數值,主要功能在保持住電路中某
個值,不必像(wire)要被驅動才能改變它的內函值
內定為一個位元值 x
P.L.Lai, VLSI Testing 2009
Appendix 1-20
選用wire 或 reg 時機
 wire 必須配合 assign 來使用 ,且不能出現在always區塊
描述裡
wire a, b, c;
assign a&c;
 reg 必須放在always區塊描述裡
input [3:0] a, b;
output [3:0] c;
reg [3:0] c;
always @ (a or b)
begin
c=a+b;
end
P.L.Lai, VLSI Testing 2009
Appendix 1-21
基本單位-port
 與module外部的信號溝通
 分為輸出(output) 、輸入(input)、雙向(inout)
 如果你只有宣告input, output, inout則將被視為是wire的型態。
 如果想要維持信號到下一個clock，則需要宣告成reg的型態(序向邏
輯電路會用到)

Example
output q;
reg q;
//這樣才可以儲存資料
 Vector (向量)


wire和reg皆可宣告成向量
Example
wire [7:0] a;
//8-bit a變數
reg [40:0] address; //41-bit address變數
P.L.Lai, VLSI Testing 2009
Appendix 1-22