Scan Chain Reorder - IC-Test Lab, NCUE, Taiwan
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Transcript Scan Chain Reorder - IC-Test Lab, NCUE, Taiwan
Scan Chain Reorder
Sying-Jyan Wang
Department of Computer Science
National Chung-Hsing University
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Outline
Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work
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Outline
■
Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work
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Digital Testing
To detect manufacturing defects
Apply test patterns and observe
output responses
Test patterns generated for targeted
fault models
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Scenario for Manufacture Test
TEST VECTORS
…
MANUFACTURED
CIRCUIT
…
CORRECT
RESPONSES
COMPARATOR
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CIRCUIT RESPONSE
PASS/FAIL
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Scan Test (1)
A structural design-for-testability
technique
Storage elements are not directly
accessible
Scan test provides an easy way for
test access
Apply test patterns to circuit under test
(CUT)
Read output responses from CUT
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Scan Test (2)
Sequential circuit
FFs are neither controllable nor observable
Primary
Input
Combinational Logic
Primary
Output
F
F
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Scan Test (3)
Normal signal path: parallel load
Primary
Input
Combinational Logic
Primary
Output
F
F
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Scan Test (4)
In scan mode: a shift register
Primary
Input
Combinational Logic
Primary
Output
Scan out
(SO)
F
F
Scan in
(SI)
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Scan Test (5)
To enable scan test
Each scan cell has two inputs
Normal input
Scan input
All scan cells are connected into a shift register
(scan chain)
Turn a sequential test into a combinational
one
Apply test patterns directly
Observe test results directly
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Scan Chain
Normally constructed when
placement and routing are done
The order does not matter
Find out the shortest scan chain order
Traveling salesman problem (TSP)
Asymmetric TSP (ATSP)
SI and SO of a scan cell are not at the
same location
NP-complete
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Outline
Overview
■ Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work
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Scan Test for Stuck-at Faults
Order does not matter
As long as we can scan in test patterns
and scan out test responses
0
1
1
0
CUT
1010
1
0
1
0
1100
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1
0
1
0
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Minimum Wirelength Routing
Use a TSP/ATSP solver
Slow
Wirelength can be 10x with random
order
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Low-Power Testing
A great concern in recent years
Need to reduce signal transitions
The source of dynamic power in CMOS
Usually the dominant factor
Reorder scan chain to reduce
switching activity
1010
1
0
1
1100
0
1
0
0
1
1 transition only
3 transitions
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Delay Testing (1)
Require two-pattern tests
First pattern: initialization
Second pattern: launch transition
Delay test with simple scan chain
Broadside
The output response of the 1st pattern are
captured in the scan chain and become the 2nd
pattern
Skewed load
The 2nd pattern is the result of 1-bit shift of the
1st pattern
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Delay Test (2)
Broadside test
Eg. Apply v1=(1010), v2=(0100)
Primary
Input
Combinational Logic
1
0
1
0
0
1
0
0
0
1
0
0
Primary
Output
F
F
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Delay Test (3)
Skewed load
Not all test pairs possible
2n2n possible 2-pattern combinations
Only 22n possible with single scan chain
Reorder scan chain to achieve higher
fault coverage
1010
0110
1
0
1
0
NOT POSSIBLE!!
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1100
1
0
1
0
0
1
1
0
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Hold Time Violation
Not enough propagation delay
between adjacent flip-flops in a
sequential circuit
Double latching
Possible solution
Reorder scan cells to introduce extra
delay
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Outline
Overview
Scan chain order: does it matter?
■ Cluster-based reordering for
lower-power BIST
Experimental results
Future work
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Overview
Goal: Reduce BIST power
Approach
Include a smoother to reduce switching
activity in test pattern generator (TPG)
Use scan chain reordering to recover lost
fault coverage
Simple reordering algorithm
Wirelength should not increase too much
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Overall Architecture
Single scan chain
PRPG
Smoother
Internal scan chain
ORA
TPG
CUT
multiple scan chain
P
R
P
G
P
h
a
s
e
s
h
i
f
t
e
r
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Smoother
Internal scan chain 1
Smoother
Internal scan chain 2
.
.
.
.
.
.
.
.
O
R
A
Smoother
Internal scan chain k
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Smoother
4-state (2bit)
smoother
n-state smoother
8-state (3bit)
smoother
1/1
1/0
1/1
S1
0/0
1/1
0/1
1/1
0/1
S1
1/0
S5
0/1
S2
S0
0/1
1/1
0/1
0/0
S4
S0
0/0
0/0
0/1
0/0
0/0
S0
1/0
S3
S2
1/0
Sn/2
S6
0/0
1/1
.
.
.
1/0
1/1
0/0
0/1
.
.
.
1/0
1/0
0/1
0/0
Sn/2–1
1/1
0/1
1/0
1/1
Sn–1
S3
S7
1/0
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A Simple Implementation of the
n-state smother
in
u
C
Divide-by-n/2
Up-Down Counter
C0
q
T
q
d
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Estimation of Power Reduction
Probability of signal transition of an
n-state smoother
P( 01) (10 )
2
2
n2 n
Compute from Markov chain model
Estimation of dynamic power
2-bit (4-state ) smoother: 1/3
3-bit (8-state) smoother: 1/10
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Fault Coverage
Smoothed patterns are less random
May create repeated patterns and reduce
fault coverage
101010100101100
PRPG
2-bit smoother
000000011110000
3-bit smoother
000000000000000
Required test cube:
Reorder scan chain:
xxxxx01xxxxxxxx
xxxxx0x1xxxxxxx
NO MATCH!
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MATCH 2-bit smoother
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Cluster-Based Scan Chain Reorder
Layout surface divided into clusters
Reorder limited in single cluster
Snake-like global routing
Multiple scan chains
Single scan chain
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Example
Routing s15850
611 scan cells
1 cluster
256 clusters
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Silicon Ensemble
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Optimal Cluster Size
Is there an optimal cluster size?
Observation
Large clusters--long vertical connection
Small clusters--more horizontal crossings
How to find optimal cluster size
Find an expression of total wirelength
Take its derivative with respect to cluster
size c
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Estimate Wirelength in a Cluster (1)
Two types of order
Random order
CL2
CL1
sc4
sc1
sc5
sc2
sc3
Sorted according to x-cooridnate
CL1
sc1
sc2
sc3
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Estimate Wirelength in a Cluster (2)
How to estimate the distance
between two cells
Manhattan distance
Horizontal and vertical distances are
independent
Assuming cells are randomly distributed
w
sc1(X1, Y1)
h
sc2(X2, Y2)
(0, 0)
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Estimate Wirelength in a Cluster (3)
Expected vertical distance between
two cells
E Y1 Y2
h
0
h
0
1
h
y1 y2 2 dy 2 dy1
h
3
Expected horizontal distance between
two cells
Random order: w/3
Sorted order
Summation of all horizontal distances: w
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Estimate Wirelength in a Cluster (4)
Random order
N: # cells, c2: #clusters
1
h N
w h
l 2 w 2 1
3 c
3
2
1
H N
W H
W 2 1
c
3 c
3c
Sorted order
1 h N
h
N H W
l 2 2 1 w 2
3
c 3c c
2 3 c
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Optimal Number of Clusters (1)
Random order
N
2W
2
W H
c
Assuming H W, N/c2 1
Sorted order
N 3W
2
H
c
Assuming H W, N/c2 3
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Optimal Number of Clusters (2)
Reordering algorithm
Larger clusters give better results
Almost no reordering when N/c2 1
Choose sorted order if no special order is
preferred
Optimal cluster size
2 N/c2 3
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Outline
Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
■ Experimental results
Future work
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Experimental Results—Wire Length
(1)
2-bit smoother
Wire length (mm)
1000
100
10
0.1
1
10
100
1000
10000
Average cells per cluster
S5378
S9234
S13207
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S15850
S38417
S38584
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Experimental Results—Wire Length
(2)
3-bit smoother
Wire length (mm)
1000
100
10
0.1
1
10
100
1000
10000
Average cells per cluster
S5378
S9234
S13207
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S15850
S38417
S38584
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Experimental Results—Fault
Coverage (1)
Test efficiency (%)
2-bit smoother
100
99
98
97
96
95
94
93
0.1
1
10
100
1000
10000
Average cells per cluster
S5378
S9234
S13207
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S15850
S38417
S38584
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Experimental Results—Fault
Coverage (2)
Test efficiency (%)
3-bit smoother
100
99
98
97
96
95
94
93
92
91
90
89
88
87
0.1
1
10
100
1000
10000
Average cells per cluster
S5378
S9234
S13207
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S15850
S38417
S38584
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Optimal Number of Cells per
Cluster
Circuit
WL (mm)
-- SE
#cluster
S641
2.71
36
S713
2.67
S953
#cells/cluster
2-bit smoother
3-bit smoother
GS
WL (mm)
Red (%)
GS
WL (mm)
Red (%)
1.50
2
2.83
-4.24
3
2.84
-4.58
36
1.50
4
2.90
-7.93
10
2.90
-7.93
3.30
16
2.81
3
3.68
-10.33
9
3.69
-10.57
S1196
4.74
16
2.00
2
5.08
-6.69
7
5.09
-6.88
S1423
5.70
36
2.53
1
6.04
-5.53
3
6.04
-5.63
S5378
14.57
100
2.14
4
15.78
-7.67
4
15.77
-7.61
S9234
22.68
100
2.47
1
23.21
-2.28
8
23.75
-4.51
S13207
45.22
256
2.73
3
44.74
1.06
6
45.49
-0.59
S15850
53.40
256
2.39
10
51.97
2.68
2
50.98
4.53
S38417
136.94
576
2.89
1
123.3
9.96
6
125.72
8.19
S38584
187.89
576
2.54
10
177.82
5.36
7
178.14
5.19
SE: Silicon Ensemble
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Test Efficienct
Circuit
TL
Test Efficiency (%)
Markov
Source
BIST
LFSR
2-bit smoother
3-bit smoother
SE
Optimal Cluster
SE
Optimal Cluster
S9234
72848
98.52
95.02
93.46
95.47
83.39
92.00
S13207
40677
97.88
98.90
92.73
97.84
83.64
87.72
S15850
37767
98.31
96.41
93.47
97.69
90.62
92.79
S38417
81984
95.42
97.20
94.79
95.96
93.5
94.47
S38584
82055
98.36
99.76
95.29
99.23
90.35
95.82
Average
-
97.70
97.46
93.95
97.24
88.3
92.56
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Comparison of Average Power
Circuit
#scan
cells
TL
FC (%)
2-bit smoother*
LFSR FC (%) FC (%)
AP
SE
Opt.
Red
cluster
(%)
3-bit smoother*
S641
54
4096
97.42
94.19
95.91
57.41
87.31
S713
54
4096
91.94
87.99
89.88
58.15
S953
45
8192
98.99
86.41
97.97
S1196
32
4096
95.49
82.63
S1423
91
4096
97.89
S5378
214
65536
S9234
247
S13207
AP
Red
(%)
FC (%)
AP
Red
(%)
90.75
85.65
89.64
36.9
83.70
83.70
86.36
93.34
37.8
55.47
54.26
80.17
84.95
85.61
58.7
92.71
56.58
59.40
78.72
85.40
95.87
30.2
95.40
98.59
57.25
88.75
96.29
85.09
97.08
49.7
98.96
97.91
98.56
58.51
90.26
95.50
84.75
97.08
44.0
131072
89.67
87.91
91.40
59.37
77.49
86.78
85.53
91.63
55.7
700
40677
97.42
91.25
96.37
62.67
82.17
86.24
87.39
-
-
S15850
611
37767
93.06
90.12
94.43
58.21
87.27
89.44
84.96
-
-
S38417
1664
81984
96.67
94.26
95.42
60.73
92.97
93.93
84.93
-
-
S38584
1464
82055
95.70
91.05
95.00
60.87
86.14
91.58
84.81
-
-
-
95.75
90.83
95.11
58.66
80.88
88.46
85.44
92.89
44.71
Average
*Full scan; : only state vectors are scanned
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FC (%) FC (%)
SE
Opt.
cluster
LT-RTPG (k=3)
43
Peak Power
Capture-cycle power is not reduced
Still provide some improvement
PP Red (%)
Circuit
2-bit smoother
3-bit smoother
S5378
13.31
11.64
S9234
13.75
16.68
S13207
12.65
19.96
S15850
13.60
20.23
S38417
13.78
19.24
S38584
13.12
18.01
Average
13.37
17.63
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Outline
Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
■ Future work
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45
Conclusion
Scan chain reorder is very effect to
deal with
Test power
Scan-based delay test
Fault coverage in BIST
Need to consider
Physical design infromation
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Future Work
Fast reordering algorithm for delay
test
Integrate reordering algorithm,
considering
Test power
Delay test coverage
Wire length
Other issues
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THE END
Thank You!
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