Transcript ECE 353 Lesson Slides

ECE 353
Introduction to
Microprocessor Systems
Week 13
Michael G. Morrow, P.E.
Topics
Serial I/O
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Serial data transfer concepts
Asynchronous and synchronous transfers
UARTs
 UART Interrupts
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Circular buffering
RS-232 and flow control
ADuC7026 Serial Peripherals
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UART
SPI
I2C
Serial I/O Concepts
Serial communication transmits data one bit
at a time.
Why?
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Data transfers over long distances
Reduced pin and interconnection count
Easier to route with switches
Eliminates parallel bus skew issues
Terminology
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Communications channel
Simplex vs. duplex
Transmission rates
Information codes
Data Frames
Serial Communications Concepts Morse Code
A
B
C
D
E
F
G
H
I
J
K
L
M
.-...
-.-.
-..
.
..-.
--.
....
..
.---..-..
--
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
-.
--.--.
--..-.
...
......--..-.---..
1
2
3
4
5
6
7
8
9
0
/
+
=
.---..--...-.........
-....
--...
---..
----.
-----..-.
.-.-.
-...-
.
,
?
(
)
"
_
'
:
;
$
.-.-.--..-..--..
-.--.
-.--.-.....-..-.
..--..----.
---...
-.-.-.
...-..-
Asynchronous vs. Synchronous
Asynchronous Communication
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No common clock signal between
transmitter and receiver
Synchronization must be established on a
per frame basis
Example – RS232
Synchronous Communication
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Clock is transmitted in addition to data, or
is recovered from data signal
Often includes a framing signal as well
Example – I2S
Asynchronous Data Transfer
RS-232 signal phases
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IDLE
Idle
Start bit
Data
Parity
Stop bit – channel returns to idle condition
Idle or Start next frame
START
D0
D1
D2
D3
D4
D5
D6
P
STOP
IDLE or
START
UARTs
Universal Asynchronous ReceiverTransmitter
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Basic UART construction
Practical UARTs
 Complex I/O device functionality encapsulated
behind a register interface
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Control
Status
Data
 16550-class UART Organization
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FIFOs
MODEM control signals
UART Interrupts
UARTs often can generate interrupts for a
number of conditions
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Receive data ready
Receive data error
 Framing, parity, overrun
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Modem signal status changes
Transmitter buffer and/or shifter empty
 Issues using the transmit interrupt
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Edge versus level interrupts
Loading the transmitter queue
Circular Buffering
Implement simple FIFO queueing in software
to minimize data movement.
Some CPUs (especially DSPs) implement
circular addressing modes in hardware for
speed.
RS-232
RS-232 is one of many physical-level
standards for serial communications.
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Selected serial communications standards
RS-232 defines many aspects of the serial
data channel
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Equipment definitions
Connector construction and pin-outs
Modem control signals
Signal levels
RS-232 line drivers and receivers
Flow Control
A serial channel may deliver data faster
than the receiving device can process.
Flow control gives the receiver a way to
signal the transmitter to stop
transmission.
Flow control can be implemented as
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Software
 XON/XOFF flow control protocol
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Hardware
 RTS/CTS
ADuC7026 Serial Peripherals
There are 4 serial peripherals on the ADuC7026;
a UART and 3 synchronous ports (SPI and I2C)
There are ten pins that are used by the serial
peripherals in two modes
ADuC7026 UART
COMCON0
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Basic frame configuration
Baud rate
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Basic baud rate divider
Fractional baud rate divider
ADuC7026 SPI Port
The Serial Peripheral Interface (SPI) port can be
configured as a master or slave (shown below)
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SPI consists of 2 unidirectional data lines, a clock line,
and a chip select line
The master generates the clock and select signals, so
it controls when/if transfers occur
ADuC7026 I2C Ports
The Inter-Integrated Circuit (I2C) ports can
operate as master or slave
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I2C supports multi-master buses using just 2
bidirectional lines (clock and data)
 Both use open-drain drivers and pull-up resistors
 Collisions can occur without damage – recognized when a line
will not return high after it is released
Wrapping Up
Quiz #3 on Thursday, May 3rd at 7:15pm
in 2255EH
Homework #7 is due Friday, May 11th
Final Exam on Wednesday, May 16th, at
12:25pm in room 2255EH.
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Coverage is over all course material.
Asynchronous Communications RS232 Framing
What do you need to know in order to figure
out what the data is?
Back
Synchronous Communications
Back
frame
Clock Recovery
1
1
0
1
1
1
1
1
0
1 Raw data
0
+V
1
0
1
1
1
1
1
0
1
RZ, bipolar
1
0
1
1
1
1
1
0
1
NRZ, Manchester
-V
+V
-V
Back
Serial Communications Standards
Back
RS-232 Connectors
Back
RS-232 Signal Levels
Data signals are
shown. Control
signals have
opposite
polarity.
Back
MAX221
Back
16550-Class
UART
Back
16550-Class UART Registers
Back
Basic UART Construction
Transmitter
ready
wr
control
unit
data bus
load
data holding register
load
1
data
shift register
serial data out
shift
clock
clock routing not shown for clarity
Receiver
shift register
serial data in
shift
load
control
unit
Back
ready
data
data holding register
rd
data bus