Transcript FPGA Power Reduction Using Configurable Dual-Vdd

Stochastic Current Prediction Enabled Frequency
Actuator for Runtime Resonance Noise Reduction
Yiyu Shi*, Jinjun Xiong+, Howard Chen+ and Lei He*
*Electrical Engineering Dept., University of California, Los Angeles
+IBM
T. J. Watson Research Center, Yorktown Heights, NY
This paper is supported in part by an NSF CAREER award
CCR0306682 and a UC MICRO grant sponsored by Actel and Fujitsu.
Outline
 Background on Resonance Noise
 Algorithm
 Experimental Results
 Conclusions
Power Supply Noise Analysis
resonance between onchip capacitance and
package inductance
H(jw)
resonance
frequency fres
~100MHz
I(jw)
ω0
frequency
Important Characteristics of Resonance Noise
 Resonance noise is significant when the spectrum of load current
has harmonic components close to the resonance frequency.

It can be reduced by changing the spectrum of the load current such
as changing the voltage or clock frequency
 Usually occurs at a frequency (50MHz~200MHz) much lower than
the clock frequency (GHz)
 Usually occurs during certain instruction loops at runtime and is
hard to detect during design-time.

It is impossible to cover the whole operation space

It is difficult to design a network that is reliable to multiple applications
Design stage techniques or runtime techniques?
 There are many existing approaches for high frequency
noise reduction at the design stage
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P/G network sizing [Tan:DAC’99]
Topology optimization [Erhard:DAC’92]
Decap budgeting [Shi:Iccad’07]
Decoupling trench capacitance [Garofano’07]
 However, to suppress the resonance noise effectively,
we have to do it at runtime such as

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Band-limited damping [Xu:ISSCC’07]
On-chip voltage regulator [Ang:ISSCC’00]
Single-shot transient suppressor
Retroactive or Proactive?
 All the existing runtime techniques are retroactive

They can only function after the noise increases above the
tolerance threshold

It takes quite a long time for the circuit to respond to the noise
 A better approach can be to suppress the noise before it
actually happens (proactively)

Accurate and efficient prediction of the load currents in the future

Runtime adjustment based on the prediction results.
 In this paper, we use the clock frequency actuator

Adjust clock frequency dynamically to avoid resonance
frequency
Resonance Noise Suppression by Frequency Actuator
H(jw)
resonance frequency fres
~100MHz
I(jw)
ω1 ω0
frequency
Outline
 Background on Resonance Noise
 Algorithm
 Experimental Results
 Conclusions
Overview of the algorithm
 We gather the current data from the on-chip dynamic current
sensors.

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The load currents are modeled as triangular waveforms with uniform
rising and falling time.
Only peak value of the currents need to be recorded.
 Based on the data, we can apply linear filter and predict the
load current in the coming a few clock cycles.

We use two kinds of filters (predetermined linear filter and adaptive filter)
to allow tradeoff between accuracy and hardware cost.
 Together with the RLC model of the P/G network and package,
we can compute the noise profile at all ports.
 Decide the optimal frequency according to the predicted load
currents to minimize the harmonic component at resonance
frequency
Predetermined Filter
 We model the peak currents as a generalized Markov stochastic
process over different clock cycles.
 At clock cycle k, given M peak current data with L clock cycles
interval Ik, Ik-L, Ik-2L, Ik-3L, … Ik-ML, we want to predict the peak current
L clock cycles ahead Iˆk L
 From the field of signal processing, we have
Iˆk  L 
M 1

i 0
i
I k iL
filter coefficients obtained
from training data
 Predetermined filter has smaller complexity to build. It has larger
prediction error, but with guaranteed convergence.
 To improve accuracy, we may adjust ψi dynamically at runtime
Adaptive filter
Adaptive Filter
 Ik-L, Ik-2L, …., Ik-ML are the history peak current data
 Ik is the predicted peak current
 Ψ1, k-1, Ψ2, k-1, …, ΨM, k-1 are the adaptive filter coefficient
 δΨ1, k-1, δΨ2, k-1, …, δΨM, k-1 are the correction for the adaptive filter coefficient
 Adaptive filter is more complex. It has less prediction error, but may not
converge.
Optimal Frequency Selection
 We can predict peak currents in future L-1 clock cycles using the
history data in M*L clock cycles by the two filters as
 The detailed current waveform can then be recovered under the
triangular waveform assumption as
unit triangular waveform
 The optimal clock frequency T can then be determined in two steps
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First analyze the spectrum of u(t) for each permissible clock period T
Then select the one that has minimum value at the resonance frequency.
Outline
 Background on Resonance Noise
 Algorithm
 Experimental Results
 Conclusions
Current Prediction Results
 LMS adaptive prediction has less prediction error in general
 Predetermined filter can always guarantee the convergence
Resonance Noise Reduction Comparison
 Compared with the baseline model without frequency actuator

the retroactive approach can only reduce the max noise by up to 14%
and reduce the mean noise by up to 33%

our proactive approach with predetermined linear filter can reduce the
max noise by up to 61%and the mean noise by up to 67%

the proactive approach with the LMS adaptive filter can reduce the max
noise by up to 79% and the mean noise by up to 87%
Latency Overhead Comparison
 The system latency for one time resonance noise violation is simulated such
that one time reboot is required in the baseline case
 The latency overhead includes
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time of potential reboot
time of clock frequency
switches to avoid resonance noise and to increase clock frequency when the
resonance is gone
time loss due to slowing down the clock
 Latency overhead is normalized with respect to the ideal latencies for the
baseline, retroactive and proactive cases.
 Compared with the latency overhead of the baseline model,
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the retroactive method reduces it by up to 35%
the proactive model with the predetermined linear filter reduces it by up to 74%
the proactive model with the LMS adaptive filter reduces it by up to 93%.
Area Overhead Comparison
 We also compare the gate count from Cadence Encounter RTL
Compiler
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The gate count overhead is only around 0.05%-0.4%
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The actuator based on adaptive filter requires about 2-4X more gates to
implement than that based on the predetermined filter
Impact of the Number of Sensors

The noise reduction is almost the same when the number of current sensors is
greater than 5%of the total number of system ports, which translates to 10 − 100
current sensors for a leading chip.

This suggests that there is no need to place many sensors for the measurement.
Conclusions
 We develop a novel stochastic method to predict the future current
load based on the knowledge of existing current profile.
 A proactive frequency actuator is proposed to suppress resonance
noise
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on-chip programmable PLL
dynamic power supply current sensors
 We develop an efficient controlling algorithm to judiciously select the
runtime clock frequency so that
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the resonance noise is contained below the tolerance bound
The impact on chip performance is minimum
 Compared with baseline design without frequency actuator,
experimental results show that significant resonance noise reduction
can be achieved.
Thank you!