Transcript ReTiS Lab

Design and Analysis of
Real-Time Software
REal TIme System Laboratory
Scuola Superiore S.Anna
G. Lipari
E. Bini
Ericsson Lab Italia
C. Vitucci
Outline
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Introduction to RT embedded systems
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characteristics
problems
state of the art
RT system research at Retis Lab
Goal of this research
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Methodology
Phases
Goal of this research
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Methodology for the design and analysis of
Real-Time Embedded applications to be
used in all phases of development
Starting Point
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Real Time embedded applications
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car controller
hand-held computers
cellular phone
next generation cellular phones (UMTS)
wearable computers
etc.
The target application
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telecommunication control board
RT embedded applications
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Limited resources
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memory
CPU speed
power consumption
Dedicated HW
Temporal constraints
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Applications must react to external environment in a
timely manner
Internal constraints (buffer size, interrupt handling, etc.)
RT design and analysis
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Support temporal determinism:
 providing kernel-level services
• priority-based schedulers
• bounded delay on system calls
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providing tools for off-line analysis
• a tool for specification in a formal (or semi-formal)
language
• a tool for timing analysis
• a tool for testing
Application model
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Application
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A task can be activated
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on a single processor there are low-level control tasks
(driver ATM etc.) and high-level control tasks (signaling)
need to verify the temporal constraints on every
task/activity
periodically (time driven)
by external events (event driven)
Tasks communicate through messages
RTOS and HW
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OSE Delta
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currently used in Ericsson for developing software for
RT embedded applications
based on a message passing communication mechanism
HW
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usually, a single processor board
many different processor can be used
performance strongly depends on the HW
Application model
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Unit -> set of tasks
HW
Temporal constraints
Period =
5 msec
Deadline =
150 msec
HW
MIT = 10 msec
State of the art
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In the engineering practice
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no a-priori timing analysis is done
low-level control tasks are directly coded in C or
assembler
often, the code of high-level control tasks is automatically
generated by tools that do not consider temporal
constraints
temporal constraint are verified only during the testing
phase
State of the art
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RT Analysis
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RT research focused on time-driven control applications
• schedulability conditions for periodic task sets
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Few research papers on RT analysis of reactive (event
driven) systems
Commercial tools: Time Wiz
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Rate Monotonic analysis
non-std notation for specification
State of the art: RT notations
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Existing notations
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UML is a good candidate notation
A preliminary proposal to OMG for a standard RT
extension to UML has been made in Aug. 2000
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HRT-HOOD (used in aerospace applications)
ROOM (from Object Time, now Rational Software)
Not suitable for our purposes
proponents: TimeSys, I-Logix, Rational Software, etc.
http://www.omg.org/meetings/schedule/UML_Profile_for_Scheduling_RFP.html
Problems
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Few tools integrate specification and analysis
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The greatest problem is to estimate the worst case
computation time of every activity
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Time Wiz of TimeSys is one of the few
strongly depends on the HW
existing tools cover a narrow range of HW configurations
There is the need for a tool that covers the entire development
cycle
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at design time, with a proper RT notation
after development, with a RT analysis
Summary
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Many different tools
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for RT-analysis (Time Wiz)
for RT specification (Rational Rose RT)
for WCET analysis (VCC)
no easy-to-use off-the-shelf solution
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there is the need to integrate different of technologies
 specification of RT systems
 RT analysis
 WCET computation
 etc.
Research at Retis Lab
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ASI project
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Intecs
definition of a HRT-UML notation
enhancing UML-nice with RT-analysis
MADESS project
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Parades, Magneti Marelli, ST microelectronics
RT kernel for embedded controllers with minimal memory
requirements
RT kernel for multi-processor system-on-a-chip
Goal of this research
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A methodology for the design and analysis of RT
embedded applications
Code analizer
Testing
Specification
(RT-UML)
Code
templates
Implementation
Consistency
check
RT analysis
WCET
Phases
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Model of a OSE-Delta process
Mapping to the appropriate RT-UML notation
RT analysis on the model
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consistency check
timing analysis
priority assignment
Integrating WCET computation