Programmable and Steering Logic

Chapter #6: Sequential Logic Design

6-1

Chapter Overview

• Sequential Networks

Simple Circuits with Feedback R-S Latch J-K Flipflop Edge-Triggered Flipflops

Programmable and Steering Logic • Timing Methodologies

Cascading Flipflops for Proper Operation Narrow Width Clocking vs. Multiphase Clocking Clock Skew

• Realizing Circuits with Flipflops

Choosing a FF Type Characteristic Equations Conversion Among Types

• Metastability and Asynchronous Inputs • Self-Timed Circuits

6-2

Sequential Switching Networks

X1 X2 .

.

Xn Switching Network Z1 Z2 .

.

Zm transistor Combinational Logic Clock State Combinational Logic Lights and time control

Programmable and Steering Logic

Circuits with Feedback: Some outputs are also inputs Traffic Light Controller is a complex sequential logic network Sequential logic forms basis for building "memory" into circuits These memory elements are primitive sequential circuits 6-3

Sequential Switching Networks

Simple Circuits with Feedback Programmable and Steering Logic

Primitive memory elements created from cascaded gates Simplest gate component: inverter Basis for commercial static RAM designs Cross-coupled NOR gates and NAND gates also possible "1" "0" Cascaded Inverters: Static Memory Cell

LD A \LD LD \LD Z

Selectively break feedback path to load new value into cell 6-4

Sequential Switching Networks

Inverter Chains

1 0 1 A B C D 0 E

Programmable and Steering Logic

0 X

Odd # of stages leads to ring oscillator Snapshot taken just before last inverter changes duty cycle : % of time singal is high during its period Output high propagating thru this stage Timing Waveform:

Period of Repeating Wavef orm (

tp

) Gate Delay (

td

)

tp = n * td n = # inverters

C D E A (=X) B 0 1 0 1 0 1

6-5

Sequential Switching Networks

Inverter Chains Programmable and Steering Logic

Time 1 1 1 1 1 0 0 0 0 0 X 0 0 0 0 0 1 1 1 1 X X 1 1 1 1 1 0 0 0 X X X 0 0 0 0 0 1 1 X X X X 1 1 1 1 1 0 Propagation of Signals through the Inverter Chain X X X X X 0 0 0 0 0 1 6-6

Sequential Switching Networks

Cross-Coupled NOR Gates

R R S Q

Programmable and Steering Logic

Just like cascaded inverters, with capability to force output to 0 (reset) or 1 (set) S Timing Waveform

Reset

R S Q \ Q

Hold

\Q

Set Reset Forbidden State Set

100

Forbidden State Race

6-7

Sequential Switching Networks

State Behavior of R-S Latch

S 0 0 1 1 R 0 1 0 1 Q hold 0 1 unst able

Q Q 0 1 Truth Table Summary of R-S Latch Behavior

Programmable and Steering Logic

Q Q 0 0 Q Q 1 0 Q Q 1 1 6-8

Sequential Logic Networks

Theoretical R-S Latch State Diagram Programmable and Steering Logic

SR = 0 1 SR = 00, 01 Q Q 0 1 SR = 1 1 SR = 00, 10 SR = 1 0 Q Q 1 0 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 Q Q 0 0 SR = 1 0 SR = 0 0 SR = 0 0, 11 Q Q 1 1 stays for very short time 6-9

Sequential Logic Networks

Observed R-S Latch Behavior Programmable and Steering Logic

SR = 00, 01 Q Q 0 1 SR = 1 1 SR = 00, 10 SR = 1 0 Q Q 1 0 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 Q Q 0 0 SR = 0 0 SR = 0 0 Very difficult to observe R-S Latch in the 1-1 state Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" 6-10

Input

Sequential Switching Networks

Definition of Terms

T su T h

Programmable and Steering Logic Clock:

Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level

Setup Time (Tsu)

Minimum time before the clocking event by which the input must be stable

Cloc k

There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

Hold Time (Th)

Minimum time after the clocking event during which the input must remain stable 6-11

Sequential Switching Networks

Level-Sensitive Latch

aka Gated R-S Latch

Programmable and Steering Logic

Schematic: any level change is propagated

\ S \ Q \ R \enb Q

Timing Diagram:

Set Reset

6-12

Sequential Switching Networks

Latches vs. Flipflops Programmable and Steering Logic Input/Output Behavior of Latches and Flipflops

Type When Inputs are Sampled When Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) 6-13

Sequential Switching Networks

Programmable and Steering Logic

7474

D Q Clk Pos itive edge-triggered f lip-f lop

7476

D Q C Clk Lev el-sens itive latc h

Bubble here for negative edge triggered device Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted Timing Diagram:

D Clk Q 7474 Q 7476

Behavior the same unless input changes while the clock is high

6-14

Sequential Switching Elements

Programmable and Steering Logic Typical Timing Specifications: Flipflops vs. Latches

74LS74 Positive Edge Triggered D Flipflop • Setup time • Hold time • Minimum clock width • Propagation delays (low to high, high to low, max and typical)

D Clk Q T su 20 ns T h 5 ns T w 25 ns T pl h 25 ns 13 ns T su 20 ns T h 5 ns T phl 40 ns 25 ns

All measurements are made from the clocking event that is, the rising edge of the clock 6-15

Sequential Switching Networks

Programmable and Steering Logic Typical Timing Specifications: Flipflops vs. Latches

74LS76 Transparent Latch

D T su 20 ns T h 5 ns

• Setup time • Hold time • Minimum Clock Width • Propagation Delays: high to low, low to high, maximum, typical data to output clock to output

Clk Q T w 20 ns T plh C » Q 27 ns 15 ns

from clock change to output change

T plh D » Q 27 ns 15 ns

from input change to output change Measurements from falling clock edge or rising or falling data edge

T su 20 ns T h 5 ns T phl C » Q 25 ns 14 ns T phl D » Q 16 ns 7 ns

6-16

Sequential Switching Elements

R-S Latch Revisited

Truth Table: Next State = F(S, R, Current State)

Programmable and Steering Logic

Derived K-Map:

SR Q ( t ) 0 00 0 01 0 11 S 10 X 1 1 1 0 X 1 R

Characteristic Equation: Q+ = S + R Q t S R Q R-S Latch Q+ 6-17

Sequential Switching Networks

J-K Flipflop

How to eliminate the forbidden state?

Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle

K J

Programmable and Steering Logic

R S R-S latc h \ Q Q \ Q Q

Characteristic Equation: Q+ = Q K + Q J 6-18

J K Q \ Q

Sequential Switching Networks

J-K Latch: Race Condition Set Reset Programmable and Steering Logic

100

Toggle

Race Condition Race : toggle signal asserted while the output change Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop 6-19

Sequential Switching Network

Master/Slave J-K Flipflop

Master Stage

K J R S R-S Latc h \Q Q \P P

Programmable and Steering Logic

Slave Stage

R S R-S Latc h \Q Q \Q Q Clk

Sample inputs while clock high Sample inputs while clock low Uses time to break feedback path from outputs to inputs!

Set Reset 1's Catc h T oggle 100 J K Clk P \ P Q \ Q Master output s Slav e output s

Correct Toggle Operation 6-20

Sequential Switching Networks

Edge-Triggered Flipflops Programmable and Steering Logic

1's Catching: a 0-1-0 glitch on the J or K inputs leads to a state change!

forces designer to use hazard-free logic Solution: edge-triggered logic

Clk=1 D D 0 R Holds D when cl ock go es l ow Q

Negative Edge-Triggered

Q 0 S Holds D when cl ock go es l ow

holding state D flipflop 4-5 gate delays setup, hold times necessary to successfully latch the input

D D

Characteristic Equation: Q+ = D Negative edge-triggered FF when clock is high 6-21

Sequential Switching Network

Edge-triggered Flipflops

Step-by-step analysis

Programmable and Steering Logic

D D D R 0 4 3 D D R 6 Clk=0 Q Clk=0 Q Q D S D D 2 S D 5 Q D D

Negative edge-triggered FF when clock goes high-to-low data is latched

D' D' ° D 1 0

Negative edge-triggered FF when clock is low data is held D is changed gate 2,4,5 are holding their values 6-22

Sequential Switching Networks

Positive vs. Negative Edge Triggered Devices Programmable and Steering Logic

100 D Clk Q pos \ Q pos Q neg \ Q neg

Positive Edge Triggered

Inputs sampled on rising edge Outputs change after rising edge

Positive edge- t riggered FF Negativ e edge- t riggered FF

Negative Edge Triggered

Inputs sampled on falling edge Outputs change after falling edge

Toggle Flipflop

Formed from J-K with both inputs wired together 6-23

Sequential Switching Networks

TTL Latch and Flip-Flop Components 7473 : JK Flip-Flop with active low clear 7473A : Negative Edge-Triggered JK 7474 : D Flip-Flop with clear and preset What if you need a negative edge triggered D Invert the clock signal into 7474 Use 7473A and wires J and K together

Programmable and Steering Logic

6-24

Timing Methodology

Programmable and Steering Logic Overview

• Set of rules for interconnecting components and clocks • When followed, guarantee proper operation of system • Approach depends on building blocks used for memory elements

For systems with latches:

Narrow Width Clocking Multiphase Clocking (e.g., Two Phase Non-Overlapping)

For systems with edge-triggered flipflops:

Single Phase Clocking • Correct Timing: (1) correct inputs, with respect to time, are provided to the FFs (2) no FF changes more than once per clocking event 6-25

Timing Methodologies

Programmable and Steering Logic Cascaded Flipflops and Setup/Hold/Propagation Delays

Shift Register S,R are preset, preclear New value to first stage while second stage obtains current value of first stage

IN D Q Q0 C Q CLK D Q Q1 C Q 100

Correct Operation, assuming positive edge triggered FF

In Q 0 Q 1 Clk

6-26

Timing Methodologies

Programmable and Steering Logic Cascaded Flipflops and Setup/Hold/Propagation Delays

Why this works: • Propagation delays far exceed hold times; Clock width constraint exceeds setup time • This guarantees following stage will latch current value before it is replaced by new value • Assumes infinitely fast distribution of the clock

In Q 0 Q 1 Clk su 20 ns T pl h 13 ns T h 5 ns T 20 ns T pl h 13 ns T h 5 ns

Timing constraints guarantee proper operation of cascaded components 6-27

Timing Methodologies

Programmable and Steering Logic Narrow Width Clocking versus Multiphase Clocking

Level Sensitive Latches vs. Edge Triggered Flipflops • Latches use fewer gates to implement a memory function • Less complex clocking with edge triggered devices

\Clk2 \ (LD • Clk1) A LD•Clk1 Clk2 Z

CMOS Dynamic Storage Element

Feedback path broken by two phases of the clock (just like master/slave idea!) 8 transistors to implement memory function but requires two clock signals constrained to be non-overlapping Edge-triggered D-FF: 6 gates (5 x 2-input, 1 x 3-input) = 26 transistors!

6-28

Timing Methodologies

Programmable and Steering Logic Narrow Width Clocking for Systems with Latches for State Generic Block Diagram for Clocked Sequential System

state implemented by latches or edge-triggered FFs

Combinational logic S t a t e Cloc k

Two-sided Constraints: must be careful of very fast signals as well as very slow signals!

Clock Width < fastest propagation through comb. logic plus latch prop delay Clock Period > slowest propagation through comb. logic (rising edge to rising edge) 6-29



Timing Methodologies

Two Phase Non-Overlapped Clocking

Clock Waveforms: must never overlap!

only worry about slow signals



1



2 1 /



1



2 /



2

Combinational Logic 1 Combinational Logic 2

Programmable and Steering Logic Embedding CMOS storage element into Clocked Sequential Logic

Note that Combinational Logic can be partitioned into two pieces C/L1: inputs latched and stable by end of phase 1; compute between phases, latch outputs by end of phase 2 C/L2: just the reverse 6-30

Timing Methodologies

Programmable and Steering Logic Generating Two-Phase Non-Overlapping Clocks Clk phase1 Single reference clock (or crystal)

Phase 1 high while clock is low Phase 2 high while clock is high

phase2

Phase X cannot go high until phase Y goes low!

Use all positive or all negative edge triggered F/F single phase clock

100 Clk Phas e 1 Phas e 2

Non-overlap time can be increased by increasing the delay on the feedback path 6-31

Timing Methodologies

The Problem of Clock Skew Programmable and Steering Logic

Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Not possible in real systems!

• logical clock driven from more than one physical circuit with timing behavior • different wire delay to different points in the circuit Effect of Skew on Cascaded Flipflops:

FF0 samples IN FF1 samples Q 0 100 In Q 0 Q 1 Clk1 Clk2

CLK2 is a delayed version of CLK1 Original State: Q0 = 1, Q1 = 1, In = 0 Because of skew, next state becomes: Q0 = 0, Q1 = 0, not Q0 = 0, Q1 = 1 6-32

Timing Methodologies

Programmable and Steering Logic Design Strategies for Minimizing Clock Skew

Typical propagation delays for LS FFs: 13 ns Need substantial clock delay (on the order of 13 ns) for skew to be a problem in this relatively slow technology Nevertheless, the following are good design practices: • distribute clock signals in general direction of data flows • wire carrying the clock between two communicating components should be as short as possible • for multiphase clocked systems, distribute all clocks in similar wire paths; this minimizes the possibility of overlap • for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high 6-33

Realing Circuits with Different Kinds of FFs

Programmable and Steering Logic Choosing a Flipflop

R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended!

however, fundamental building block of other flipflop types J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement (In,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!!

6-34

Characteristic Equations

R-S: D: J-K: T: Q+ = S + R Q Q+ = D Q+ = J Q + K Q Q+ = T Q + T Q Derived from the K-maps for Q+ = (Inputs, Q) E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q

Implementing One FF in Terms of Another

D J C K Q Q Q K J

D implemented with J-K J-K implemented with D

D Q C Q

6-35

Design Procedure

Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

Q 0 0 1 1 Q + 0 1 0 1 R X 0 1 0 S 0 1 0 X J 0 1 X X K X X 1 0 T 0 1 1 0 D 0 1 0 1

Implementing D FF with a J-K FF:

Q D 0 0 0 1 1

1) Start with K-map of Q+ = (D, Q)

1 0 1

2) Create K-maps for J and K with same inputs (D, Q)

Q + = D

3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map E.g., D = Q= 0, Q+ = 0 then J = 0, K = X

Q D 0 0 0 1 1 Q D 0 0 X 1 X 1 X X J = D 1 1 0 K = D

6-36

Design Procedure (Continued)

Implementing J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple!

Q JK J 00 01 11 10 0 0 0 1 1 1 1 0 0 1 K Q

+

= D = JQ + KQ

Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF.

6-37

Metastability and Asynchronous Inputs

Terms and Definitions Programmable and Steering Logic

Clocked synchronous circuits • common reference signal called the clock • state of the circuit changes in relation to this clock signal Asynchronous circuits • inputs, state, and outputs sampled or changed independent of a common reference signal R-S latch is asynchronous, J-K master/slave FF is synchronous Synchronous inputs • active only when the clock edge or level is active Asynchronous inputs • take effect immediately, without consideration of the clock Compare R, S inputs of clocked transparent latch vs. plain latch (level sensitive) 6-38

Metastability and Asynchronous Inputs

Programmable and Steering Logic Asynchronous Inputs Are Dangerous!

Since they take effect immediately, glitches can be disastrous Synchronous inputs are greatly preferred!

But sometimes, asynchronous inputs cannot be avoided e.g., reset signal, memory wait signal 6-39

Metastability and Asynchronous Outputs

Handling Asynchronous Inputs Programmable and Steering Logic

Async Input Clocked Synchronous System D Q Q0 D Q Clock Q1 Clock Async Input D Q Synchronizer Q0 D Q D Q Clock Q1 Clock Never allow asynchronous inputs to be fanned out to more than one FF within the synchronous system 6-40

Metastability and Asynchronous Inputs

What Can Go Wrong Setup time violation!

In Q 0 Q 1 Clk

Programmable and Steering Logic

In is asynchronous Fans out to D0 and D1 One FF catches the signal, one does not

impossible state might be reached!

Single FF that receives the asynchronous signal is a synchronizer 6-41

In

Metastability and Asynchronous Inputs

Synchronizer Failure

D Q

Programmable and Steering Logic

?

When FF input changes close to clock edge, the FF may enter the metastable state: neither a logic 0 nor a logic 1 It may stay in this state an indefinate amount of time, although this is not likely in real circuits

Logic 1

Small, but non-zero probability that the FF output will get stuck in an in-between state

Logic 0 T ime

Oscilloscope Traces Demonstrating Synchronizer Failure and Eventual Decay to Steady State 6-42

Metastability and Asynchronous Inputs

Solutions to Synchronizer Failure Programmable and Steering Logic

• reset the entire clock • the probability of failure can never be reduced to 0, but it can be reduced • slow down the system clock this gives the synchronizer more time to decay into a steady state synchronizer failure becomes a big problem for very high speed systems • use fastest possible logic in the synchronizer this makes for a very sharp "peak" upon which to balance S or AS TTL D-FFs are recommended • cascade two synchronizers • use timing strategy that is independent of the speed Asynchronous Input D Q D Q Synchronized Input Clk Synchronous System 6-43

Self-Timed and Speed Independent Circuits

Limits of Synchronous Systems Programmable and Steering Logic

Fully synchronous not possible for very large systems because of problems of clock skew Partition system into components that are locally clocked These communicate using "speed independent" protocols Clocked Subsystem Communications Signals Clocked Subsystem Request/Acknowledgement Signaling

Reques t S1 request er client mas ter Data Flow Acknow ledgement S2 provider server slav e

6-44

Self-Timed and Speed Independent Circuits

Synchronous Signaling Programmable and Steering Logic

Req Data Ac k Clk

Master issues read request; Slave produces data and acks back

Req Data W ait Clk

Alternative Synchronous Scheme: Slave issues WAIT signal if it cannot satisfy request in one clock cycle 6-45

Self-Timed and Speed Independent Circuits

Asynchronous/Speed Independent Signaling Programmable and Steering Logic

Communicate information by signal levels rather than edges!

No clock signal

4 Cycle Signaling/Return to Zero Signaling

Req Data Ac k

(1) master raises request slave performs request (2) slave "done" by raising acknowledge (3) master latches data acks by lowering request (4) slave resets self by lowing acknowledge signal 6-46

Self-Timed and Speed Independent Circuits

Alternative: 2 cycle signaling

Non-Return-to-Zero

Programmable and Steering Logic

Req Data Ac k

(1) master raises request slave services request (2) slave indicates that it is done by raising acknowledge Next request indicated by low level of request Requires additional state in master and slave to remember previous setting or request/acknowledge 4 Cycle Signaling is more foolproof 6-47

Self-Timed and Speed Independent Circuits

Self-Timed Circuits Programmable and Steering Logic

Determine on their own when a given request has been serviced No internal clocks Usually accomplished by modeling worse case delay within self-timed component

Input Req Combinational logic Output Ac k Delay

Models worst case delay e.g., if combinational logic is 5 gate levels deep, delay line between request in and ack out is also 5 levels deep 6-48

Practical Matters

Programmable and Steering Logic

Debouncing Switches bouncing : when a switch is flipped from one terminal to another it does not make a clean, solid contact solution : debouncing a switch initial setup

6-49

Practical Matters

•

Debouncing a switch

Programmable and Steering Logic

6-50

Practical Matters

•

555 programmable timer

Programmable and Steering Logic

6-51

Practical Matters

•

Free-running clock frequency of 555 timer

Programmable and Steering Logic

6-52

Chapter Summary

Programmable and Steering Logic

• Fundamental Building Block of Circuits with State: latch and flipflop • R-S Latch, J-K master/slave Flipflop, Edge-triggered D Flipflop • Clocking Methodologies: For latches: Narrow width clocking vs. Multiphase Non-overlapped Narrow width clocking and two sided timing constraints Two phase clocking and single sided timing constraints For FFs: Single phase clocking with edge triggered flipflops Cascaded FFs work because propagation delays exceed hold times Beware of Clock Skew • Asynchronous Inputs and Their Dangers Synchronizer Failure: What it is and how to minimize its impact • Speed Independent Circuits Asynchronous Signaling Conventions: 4 and 2 Cycle Handshakes Self-Timed Circuits 6-53