Chapter 4. Basics of Device Fabrication

MOSFET

The source contact is used as the voltage reference.

The conductance of the channel can be modulated by varying the gate voltage.

The source-to-drain path corresponds to two p-n junctions connected back to back.

CMOS

Invention of MOSFET

Dawon Kahng was born on May 4, 1931 in Seoul. He received B.S. degree in Seoul National University in 1955 and Ph.D. degree from Ohio State University in 1959. He died on May 28, 1992 in New Jersey.

In 1959, he invented the MOSFET in collaboration with Ernesto Labate and Martin M. (John) Atalla at Bell Labs. It was the first successful insulated-gate field-effect transistor (FET) that overcame the "surface states" that blocked electric fields from penetrating into the semiconductor material. Investigating thermally grown silicon-dioxide layers, they found these states could be markedly reduced at the interface between the silicon and its oxide in a sandwich structure of metal-oxide-silicon. In 1960, he and M. Atalla fabricated the MOSFET using a gate insulator formed from high quality SiO 2 grown in-situ by a new high-pressure steam oxidation process. It was the first successful demonstration of MOSFET and a major milestone in semiconductor technology.

He also invented in 1967 a field effect memory, the first nonvolatile silicon memory (floating gate memory) .

Oxidation

 Oxidation – Growth of SiO 2  Function of SiO 2 by reacting Si with O.

• Insulator in a device structure • Barrier to diffusion during device fabrication  Dry oxidation • Si + O 2 → SiO 2 • Superior Si-SiO 2  Wet oxidation interface property • Si + 2H 2 O → SiO 2 + 2H 2 • Faster growth rate : suitable for thick barrier oxide

Oxidation

 Oxidation – Growth of SiO 2  Function of SiO 2 by reacting Si with O.

• Insulator in a device structure • Barrier to diffusion during device fabrication  Dry oxidation • Si + O 2 → SiO 2 • Superior Si-SiO 2  Wet oxidation interface property • Si + 2H 2 O → SiO 2 + 2H 2 • Faster growth rate : suitable for thick barrier oxide

Oxidation System

Oxidation Rate

Diffusion

 Solid state diffusion – widely used method for introducing dopant atoms into a semiconductor lattice.

 Si wafer is exposed to a solid, liquid, or gaseous source containing the desired impurity.  Two-step process • Predeposition : diffusion with the source present • Drive-in : diffusion with the source removed

Diffusion System

900 o C ~ 1200 o C  Open tube system identical to that used for oxidation.

 N 2 carrier gas is passed through a bubbler containing POCl 3 .

Ion Implantation

 Alternative means of introducing dopants and other atoms into the near surface region of a semiconductor.

 Shooting ions into the semiconductor resulting in displacement of semiconductor atoms. ⇒ A follow-up anneal (heating) is necessary to remove the crystal damage and “activate” implanted dopants.  Advantages over diffusion • Low temperature process • Very precise control of the impurity concentration • Very shallow concentration profile is obtainable.  Gaussian concentration profile • R p • ΔR p : projected range : straggle

N

(

x

)  2   ( 

R p

)

e

 ( 1 / 2 )[(

x



R p

) / 

R p

] 2

Ion Implantation System

Implantation Profile

Lithography

 Patterning of insulators or metals by selective removal of a thin film at prescribed regions across the surface of a wafer  Process flow • Photoresist(PR) coating by spinning • Prebake(or soft bake) : to drive solvent out of the resist • Exposure through a mask using UV-light • Development : removal of exposed (or unexposed) region • Hard bake : to improve resistance to the subsequent etch • Etch : wet etch by acid solution or dry etch by plasma • PR Strip : using a chemical solution or an oxygen plasma  Positive PR vs. negative PR

Lithography Process

(c) → (d)

Thin Film Deposition

 Purposes • Metallization : connecting devices • Deposition of intervening dielectric layers • Diffusion barrier : preventing interdiffusion of materials • Passivation : protecting the device or circuit from contamination.  Physical Vapor Deposition (PVD) • Evaporation, sputtering  Chemical Vapor Deposition (CVD) • LPCVD (low pressure), APCVD (atmospheric pressure), PECVD (plasma-enhanced)

Evaporation

 Source is vaporized in a vacuum chamber.

 Source material travels unimpeded to the substrate and deposits as thin film.  Hot-filament evaporation - high levels of contamination  Electron-beam evaporation - X-ray ⇒ device degradation  Not used in the production-line fabrication of modern ICs

Sputtering

 High voltage between two plates ionizes Ar gas at low-pressure.

 Ar + ions accelerated by electric field hit the source material ejecting the source atoms.

 Ejected atoms travel to the substrate and deposit to form the desired thin film.

 DC sputtering for metals  RF sputtering for insulators  Low contamination & high throughput  Chief commercial method of depositing Al and other metals

CVD

 A gaseous compound decomposes to form the thin film or a reaction between gas components takes place to form the film.

 CVD reactions take place preferentially on the surface of wafers.

 LPCVD - Good uniformity, less gas consumption, low contamination  PECVD - Low deposition temperature  CVD process produces the masking and intermetallic dielectric films.

LPCVD

CVD System

PECVD

Epitaxy

 More surface migration at higher temperature and lower pressure leads to epitaxy.  Epitaxy produces a crystalline layer that is an extension of the underlying semiconductor lattice.

 Doping of the epi-layer is controlled by introducing dopant containing gas.

Epitaxy of Different Element Films

Epitaxy of Different Element Films

Process Steps for

pn

Junction Diode

CPU Process Flow CPU Process Flow