No Slide Title
Download
Report
Transcript No Slide Title
RiceNIC: A Reconfigurable and Programmable
Gigabit Network Interface Card
Jeff Shafer, Dr. Scott Rixner
Rice Computer Architecture: http://www.cs.rice.edu/CS/Architecture
Networks are Essential!
NIC Features
Performance
Networking is an integral part of computer systems
The role of a network interface is evolving
Significant new research is changing the
hardware/software interface between the operating
system and the network interface card (NIC)
Researchers need a flexible NIC to study this field
RiceNIC is a reconfigurable and programmable Gigabit
Ethernet NIC that meets these research needs
NIC design is freely available for research/education!
NIC provides significant computation and storage
resources and allows the user to customize NIC
behavior in software and hardware.
Software Programmability
Dual 300 MHz PowerPC
processors
256 MB DDR memory
2MB SRAM (accessible
from host and NIC)
Serial port for debugging
Descriptor control system
Hardware Acceleration
MAC / DMA controllers
TCP Checksum Offloading
Hardware Event notification
RiceNIC TCP stream throughput
compared to commercial NIC
Development Platform
Device Utilization
Software Design
Avnet Virtex-II Pro Development Board
Space for future development
PowerPC processor runs custom
packet-handling firmware
Interfaces with MAC to
send/receive packets
Interfaces with DDR to store
bulk frame data
Interfaces with DMA engine
to transfer data to/from host
Custom Linux and FreeBSD
device drivers
Component
Slice Registers
9,089 / 27,392 33%
4 input LUTs
11,811 / 27,392 43%
BRAMs
51 / 136 37%
Occupied Slices 9,164 / 13,696 66%
Global Clocks
10 / 16 62%
Clock Managers
5 / 8 62%
Gate Count:
3,944,049
Serial Port
DDR
Virtex FPGA
Spartan FPGA
RJ-45 Port
Ethernet PHY
PCI Interface
Virtex FPGA Placement
System Architecture
Gigabit
Ethernet
FPGA Development Board
PHY
RS-232
Serial
Virtex FPGA
Virtex FPGA
BRAM
(32 KB)
UART
Gigabit
MAC
DDR
Controller
PLB Bus
I-Cache
(16 KB)
Front-End
DMA
Spartan FPGA
Bridge
D-Cache
(16 KB)
PowerPC 405
Embedded Processor
(300 MHz)
I-Cache
(16 KB)
D-Cache
(16 KB)
PowerPC 405
Embedded Processor
(300 MHz)
DDR
Memory
(256 MB)
Hardware
Events
Scratchpad
(2 KB)
PCI Bus (64b / 66 MHz)
Bridge
Back-End
DMA
SRAM
Controller
PCI
SRAM
(2 MB)
Ethernet
MAC
DDR
Controller
PowerPC
Processors
NIC Control
& Data Bus
PCI DMA
Engine