Transcript Document

CprE / ComS 583
Reconfigurable Computing
Prof. Joseph Zambreno
Department of Electrical and Computer Engineering
Iowa State University
Lecture #1 – Introduction
What is Reconfigurable Computing?
• configurable (adj.) – written to permit
modification by users; able to be modified or
arranged differently
• computing (n.) – the procedure of calculating;
determining something by mathematical or
logical methods
• Reconfigurable computing – a procedure of
calculating that is able to be modified by users
• Any examples?
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.2
What is Reconfigurable Computing?
• In its current usage, the term reconfigurable
computing refers to some form of hardware
programmability
• Hardware that can be customized using some physical
control points
• Goal: to adapt at the logic level to solve specific
problems
• Why do we care?
• Certain applications aren’t well suited to
general-purpose computing model
• Exponential growth in available chip resources
– what to do with them?
• Other advantages (fast time-to-market,
performance competitive with custom ASIC,
bugs can be fixed in the field)
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.3
Outline
• What is reconfigurable computing?
• Defining characteristics
• A brief history
• The density computing advantage
• Introduction to the FPGA
• Course administration and outline
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.4
What Characterizes RC?
• Parallelism customized to meet design objectives
• Logic specialization to perform a specific function
• Hardware-level adaptation of functionality to meet
changing problem requirements
xi
w1
x
+
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w2
x
+
w3
x
+
w4
x
+
CprE 583 – Reconfigurable Computing
Example: 4-tap FIR
filter [DeHon 2000]
yi
Lect-01.5
Temporal (Microprocessor) Systems
• Generalized – can perform many functions well
• Sequential – inherently constrained even with
multiple data paths
• Fixed logic – data sizes, number of
computational units, etc. cannot be changed
Ay
t2
w1
w2
w3
w4
Ax
t1
x1
x2
x3
x4
ALU
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x4  x3 // x[i-3]
x3  x2 // x[i-2]
x2  x1 // x[i-1]
Ax  Ax + 1
x1  [Ax] // x[i]
t1  w1 x x1
t2  t1 + t2
…
CprE 583 – Reconfigurable Computing
t2  w2 x x2
t1  t1 + t2
t2  w3 x x3
t1  t1 + t2
t2  w4 x x4
t1  t1 + t2
Ay  Ay + 1
[Ay]  t1
Lect-01.6
Example: Comparison Operation
A
M1: process(CLK, A, B)
begin
if rising_edge(CLK) then
if (A > B) then
H <= A;
L <= B;
else
H <= B;
L <= A;
end if;
end if;
end process;
0
H
1
<
1
L
B
0
CLK
• Specialization? Check.
• Optimization? Check.
• Parallelism??
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.7
Example: Sorting an Array
in[8] 0 1 2 3 4 5 6 7
A
B
A
B
A
B
A
B
H
L
H
L
H
L
H
L
A
B
A
B
A
B
A
B
H
L
H
L
H
L
H
L
A
B
A
B
A
B
A
B
H
L
H
L
H
L
H
L
A
B
A
B
A
B
H
L
H
L
H
L
out[8] 0 1 2 3 4 5 6 7
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CprE 583 – Reconfigurable Computing
Lect-01.8
Hardware Spectrum
Full Custom
• ASIC gives high
ASIC
Gate Array
Cost / Performance
performance at cost of
programmability
• Processor is very
programmable but not
tuned to the application
• Reconfigurable hardware
is a nice compromise
FPGA
PLD
GP Processor
SP Processor
Multifunction
Fixed Function
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.9
History of IC Technology
• 1947: First transistor (Shockley, Bell Labs)
• 1958: First integrated circuit (Kilby, TI)
• 1971: First microprocessor (4004, Intel)
• Today: six+ wire layers, 45nm feature
sizes
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.10
History of Reconfigurable Computing
• Earliest reconfigurable computer proposed in the
1960s (Gerald Estrin, UCLA) [1]
• Basic concepts well ahead of the enabling technology:
• Could only prototype a crude approximation
• The availability of high-density VLSI devices that use
programmable switches spurred current interest
• Current chips – contain memory cells that hold both
configuration and state information
• Only a partial architecture exists before programming
• After configuration, the device provides an execution
environment for a specific application
[1] G. Estrin et al., “Parallel Processing in a Restructurable Computer System,”
IEEE Trans. Electronic Computers, pp. 747-755, Dec. 1963.
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CprE 583 – Reconfigurable Computing
Lect-01.11
Moore’s Law
• Exponential rate of increase in the number of
transistors per chip - Gordon Moore, Intel [1965]
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CprE 583 – Reconfigurable Computing
Lect-01.12
Classifying Reconfigurable Systems
• Current reconfigurable computing systems can be
classified by three main design decisions [2]:
• Granularity of programmable hardware
• Low-level components with traditional ASIC design flow?
• More complex base units like multipliers, ALUs, etc.?
• Proximity of the CPU to the programmable hardware
• On the chip? On the bus? On the board? On the network?
• Capacity
• How many equivalent ASIC gates?
• How to allocate resources? Set ratios of memory to computation
to interconnect?
[2] W. Mangione-Smith et al., “Seeking Solutions in Configurable Computing,”
IEEE Computer, pp. 38-43, Dec. 1997.
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CprE 583 – Reconfigurable Computing
Lect-01.13
LUT-based Logic Element
I1 I2 I3 I4
Cout
• Each LUT operates on four
Cout
carry
logic
4-LUT
DFF
OUT
one-bit inputs
• Output is one data bit
• Can perform any Boolean
function of four inputs
4
2
• 2 = 65536 functions (4096
patterns)
• The basic logic element can be more complex
(multiplier, ALU, etc.)
• Contains some sort of programmable interconnect
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CprE 583 – Reconfigurable Computing
Lect-01.14
RaPiD DataPath
Input
Streams
Output
Streams
Memory
Custom
Function
Multiply
A
L
U
A
L
U
•
RaPiD: Reconfigurable Pipelined Datapath
•
Linear array of function units
•
Multiply
A
L
U
Memory
A
L
U
Function type determined by application
•
Function units are connected together as needed using segmented
buses
•
Data enters the pipeline via input streams and exits via output streams
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CprE 583 – Reconfigurable Computing
Lect-01.15
Coupling in a Reconfigurable System
Workstation
Coprocessor
Attached Processing Unit
Standalone Processing Unit
CPU
FU
Memory
Caches
I/O
Interface
• Some advantages of each?
• Some disadvantages?
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CprE 583 – Reconfigurable Computing
Lect-01.16
Capacity Trends
Virtex-5
550 MHz
24M gates*
Xilinx Device Complexity
Virtex-II Pro
450 MHz
8M gates*
Virtex-II
450 MHz
8M gates
Virtex-E
240 MHz
4M gates
Virtex
200 MHz
1M gates
XC4000
100 MHz
250K gates
XC2000
50 MHz
1K gates
XC3000
85 MHz
7.5K gates
1985 1987
1991
XC5200
50 MHz
23K gates
1995
Spartan
80 MHz
40K gates
Virtex-4
500 MHz
16M gates*
Spartan-3
326 MHz
5M gates
Spartan-II
200 MHz
200K gates
1998 1999 2000 2002 2003 2004
2006
Year
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CprE 583 – Reconfigurable Computing
Lect-01.17
The Density Computing Advantage
•
Claim – reconfigurable processors offer a definite advantage over
general-purpose counterparts with regards to functional density [3]
• Computations per chip area per cycle time
• Will visit this concept in more detail on Thursday
Actel ProASIC
Intel Pentium 4
[3] A. DeHon. “The Density Advantage of Configurable Computing,” IEEE
Computer, pp. 41-49, Apr. 2000.
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CprE 583 – Reconfigurable Computing
Lect-01.18
Introduction to the FPGA
• Field-Programmable Gate Arrays
• Literally, an array of logic gates that can be programmed
with new functionality in the field.
• Target Applications
• Image/video processing
• Cryptographic ciphers
• Military and aerospace applications
• What are the advantages of FPGA technology?
• Algorithmic agility / upload
• Cost efficiency
• Resource efficiency
• Throughput
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CprE 583 – Reconfigurable Computing
Lect-01.19
Introduction (cont.)
• Major players in the FPGA industry:
• Chipmakers – device families
•
•
•
•
Xilinx – Spartan, Spartan-II, Spartan-3, Virtex, Virtex-II
Actel – eX, MX, SX, Axcelerator, ProASIC
Altera – ACEX, FLEX, APEX, Cyclone, Mercury, Stratix
Atmel – AT6000, AT40K
• Software developers – CAD tools
• Synopsys – FPGA Compiler
• Mentor Graphics – HDL Designer, ModelSim
• Synplicity – Synplify, Synplify Pro
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CprE 583 – Reconfigurable Computing
Lect-01.20
FPGA Architecture
• FPGAs are composed of the following:
• Configurable Logic Blocks (CLBs)
• Programmable interconnect
• Input/Output Buffers (IOBs)
• Other stuff (clock trees, timers, memory, multipliers,
processors, etc.)
• CLBs contain a number of Look-Up Tables (LUTs) and
some sequential storage.
• LUTs are individually configured as logic gates, or can
be combined into n bit wide arithmetic functions.
• Architecture Specific
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CprE 583 – Reconfigurable Computing
Lect-01.21
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IOB
IOB
IOB
CLB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
IOB
Generic island-style
FPGA architecture
IOB
IOB
•
Programmable
interconnect mesh
IOB
IOB
•
Configurable Logic
Blocks (CLBs)
IOB
IOB
•
Input/Output Buffers
(IOBs)
IOB
•
IOB
FPGA Architecture (cont.)
IOB
IOB
IOB
IOB
IOBc
CprE 583 – Reconfigurable Computing
Lect-01.22
Example: Xilinx Virtex-II
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CprE 583 – Reconfigurable Computing
Lect-01.23
Course Administration
•
•
Professor Joseph Zambreno
Room: 327 Durham
Phone: (515) 294-3312
Email: [email protected]
Office Hours: TBD
• Course web page: http://class.ece.iastate.edu/cpre583
• WebCT (Gold) for assignment submission, online discussion, grading
•
Textbook: None required.
Will be expected to read the references listed on the course web
page for class discussion
Be skeptical! Just because something was published does not mean
it is correct or good
•
Grading
• ~4 homework assignments (25%)
• Midterm exam (25%)
• Final project (50%)
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.24
Course Project
• Perform an in-depth exploration of some area
of reconfigurable computing
• Whatever topic you choose, you must include
a strong experimental element in your project
• Work in groups of 2+ (3 if very lofty proposal)
• Deliverables:
• Project proposal (2-3 pages, middle of term)
• Project presentation (25 minutes, week 15)
• Project report (10-15 pages, end of term)
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.25
Some Suggested Topics
•
Design and implementation of X
•
•
Pick any application or application domain
Identify whatever objectives need to optimized (power, performance, area,
etc.)
• Design and implement X targeting an FPGA
• Compare to microprocessor-based implementation
•
Network processing
•
Explore the use of an FPGA as a network processor that can support
flexibility in protocol through reconfiguration
• Flexibility could be with respect to optimization
• Could provide additional processing to packets/connections
•
Implement a full-fledged FPGA-based embedded system
•
•
From block diagram to physical hardware
Examples:
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•
•
•
•
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Image/video processor
Digital picture frame
Digital clock (w/video)
Sound effects processor
Any old-school video game 
Voice-over-IP
CprE 583 – Reconfigurable Computing
Lect-01.26
Suggested Project Topics (cont.)
• Prototype some microarchitectural concept using FPGA
• See proceedings of MICRO/ISCA/HPCA/ASPLOS from
last 5 years
• Survey some recurring topic
• Compare results from simulation (Simplescalar) to
FPGA prototype results
• Evaluation of various FPGA automation tools and
methodologies
• Survey 3-4 different available FPGA design tools
• Pick a representative (pre-existing) benchmark set, see
how they fare…how well do they work?
• Analyze output designs to determine basic differences
in algorithms and methodology
• Anything else that interests you!
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.27
Previous Year’s Topics
• Fall 2006 projects:
• “FPGA Implementation of Frequency-Domain Audio
Filter Bank” (2 students)
• “Transparent FPGA-Based Network Analyzer” (2
students)
• “FPGA-Based Library Design for Linear Algebra
Applications” (2 students)
• “An Improved Approach of Configuration Compression
for FPGA-based Embedded Systems” (2 students)
• “Analysis of Sobel Edge Detection Implementations” (1
student)
• “Artificial Neural Networks on Dynamically
Reconfigurable FPGAs” (3 students)
• Papers and presentations for these are available upon
request
• We can do better!
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.28
Provisional Course Schedule
• Introduction to Reconfigurable Computing
• FPGA Technology, Architectures, and Applications
• FPGA Design (theory / practice)
• Hardware computing models
• Design tools and methodologies
• HW/SW codesign
• Other Reconfigurable Architectures and Platforms
• Emerging Technologies
• Dynamic / run-time reconfiguration
• High-level FPGA synthesis
• Novel architectures
• Weekly schedule: http://class.ece.iastate.edu/cpre583
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CprE 583 – Reconfigurable Computing
Lect-01.29
Summary
•
Reconfigurable hardware – can be customized using some
physical control mechanism
• Goal is to adapt at the logic level to solve specific problems
•
Programmable computational components and interconnect
• Certain applications are well-suited to reconfigurable hardware
• FPGA – Field-Programmable Gate Array
• More flexibility (compared to ASIC)
• Better cost efficiency (compared to ASIC)
• Greater resource efficiency (compared to CPU)
• Higher throughputs (compared to CPU)
•
Reconfigurable computing is an active area of research at Iowa
State (Arun Somani, Akhilesh Tyagi)
August 21, 2007
CprE 583 – Reconfigurable Computing
Lect-01.30