Transcript Document
Computer Architecture I: Digital Design
Dr. Robert D. Kent
Logic Design Medium Scale Integration and Programmable Logic Devices Part II
Review
• At the outset of designing a complex system, such as a modern computer or network, it is clear that design is extraordinarily difficult and computationally challenging when performed at the level of fundamental Boolean logic gates.
• For these reasons modern design approaches are based on hierarchical, component based methods.
– Leading to simplified, localized component design, – lowering of design costs, – shifting some aspects of design to the component interface (the compatibility problem).
• We now continue our study of MSI circuits to better understand this process of MSI design.
Goals
• We continue our study of simple, but functional Combinational circuits: – we continue constructing a small library of useful components – through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design – we seek to identify these components for their re-use potential – through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.
Circuit # 4 : Binary Subtractor
Circuit # 4 : Binary Subtractor
• Before proceeding to design a subtractor circuit, consider a few examples of the operation D = X - Y: • Example 1 :
Example 1 : X 0 0 1 1
-
Y 0 0 0 1 ======= D 0 0 1 0
Considered “easy” because: 1-1 = 0 is easy 1-0 = 1 is easy 0-0 = 0 is easy But .....
Circuit # 4 : Binary Subtractor
• Example 2 : – This is not straightforward – it requires the concept of “borrowing” from the column on the left.
– Use a
trick – add zero!
representation,
B = 2 L
.
Introduce a borrow constant, B. For an L-bit
Example 2 : B= 1 0 0 0 0 X 0 0 1 1
-
Y 0 1 0 1 ======= D 1 1 1 0
This is not a mathematical zero.
Rather, it is a practical zero since we only use the low-order 4 bits.
Circuit # 4 : Binary Subtractor
• Example 2 : – This is not straightforward – it requires the concept of “borrowing” from the column on the left.
– Use a
trick – add zero!
representation,
B = 2 L
.
Introduce a borrow constant, B. For an L-bit
Example 2 : B= 1 0 0 0 0
Instead of X K – Y K , we have recast this in the form B K + X K – Y K .
X 0 0 1 1
-
Y 0 1 0 1 ======= D 1 1 1 0
NOTE: By borrowing from the left, each successive borrow digit becomes a 1 until the column which forces the first borrow. This specific borrow digit has the value 2 (binary 10).
Circuit # 4 : Binary Subtractor
• Example 2 : – This is not straightforward – it requires the concept of “borrowing” from the column on the left.
– Use a
trick – add zero!
representation,
B = 2 L
.
Introduce a borrow constant, B. For an L-bit
Example 2 : B= 1 0 0 0 0
Now we note that we have already borrowed from this column (in the next-to-right column). -
X 0 0 1 1 Y 0 1 0 1 ======= D 1 1 1 0
But we also had to borrow from the next-to-left column. Hence, we borrow a ‘2’ from the left, then borrow ‘1’ from this ‘2’ to the right, the net result is to add ‘1’ to the current column. The rest of the subtraction (+2-1+0-0)=1 is easy.
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B K+1
B K refers to the amount of borrowing already performed (in order to carry out a subtraction in the next-to-right column) X K and Y K are the inputs for (X K -Y K ) and D K is the difference (within the K’th column) B K+1 refers to the amount of borrowing that must be done from the next-to-left column (in order to carry out a subtraction in the current K’th column) NOTE: It is understood that a ‘1’ denotes a borrow of ‘2’ in the current K’th column.
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B K+1 0 0 0 0 0 0 X K minuend 0 Y K subtrahend 0 D K difference
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B K+1 0 0 0 0 0 There is no need to perform a “borrow” operation.
0 X K minuend 0 Y K subtrahend 0 D K difference
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 0 K+1 0 X K minuend 0 Y K subtrahend 1 B K prior borrow 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 0 K+1 Assume that a “borrow” was required in a previous column subtraction - then we must subtract 1 from the minuend in this column.
0 X K minuend 0 Y K subtrahend 1 B K prior borrow 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1 , and then use the value 2 (!) for the minuend, X K .
2 0 X K minuend 0 Y K subtrahend 1 B K prior borrow 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 K+1 0 X K minuend 1 Y K subtrahend 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 K+1 If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1 , and then use the value 2 (!) for the minuend, X K .
2 0 X K minuend 1 Y K subtrahend 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 1 1 1 0 1 1 0 1 K+1 0 0 0 0 0 0 1 0 1 1 0 X K minuend 1 Y K subtrahend 1 B K prior borrow 0 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 K+1 If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1 , and then use the value 2 (!) for the minuend, X K .
2 0 X K minuend 1 Y K subtrahend 1 B K prior borrow 0 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 K+1 0 1 0 1 1 0 1 1 0 1 There is no need to perform a “borrow” operation.
1 X K minuend 0 Y K subtrahend 0 B K prior borrow 1 D K 0 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 K+1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 There is no need to perform a “borrow” operation.
1 X K minuend 0 Y K subtrahend 1 B K prior borrow 0 D K 0 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 K+1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 There is no need to perform a “borrow” operation.
1 X K minuend 1 Y K subtrahend 0 B K prior borrow 0 D K 0 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1 , and then use the value 2 (!) for the minuend, X K .
2 1 X K minuend 1 Y K subtrahend 1 B K prior borrow 1 D K 1 B K+1 difference next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
• The circuit expressions for the outputs are derived:
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
• The circuit expressions for the outputs are derived:
D K = X K ’Y K ’B K + X K ’Y K B K ’ + X K Y K ’B K ’ + X K Y K B K
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
• The circuit expressions for the outputs are derived:
D K = X K ’Y K ’B K + X K ’Y K B K ’ + X K Y K ’B K ’ + X K Y K B K = B K xor X K xor Y K
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 D K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 = B K xor X K xor Y K
• The circuit expressions for the outputs are derived:
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 D K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 = B K xor X K xor Y K
• The circuit expressions for the outputs are derived:
B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 D K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 = B K xor X K xor Y K
• The circuit expressions for the outputs are derived:
B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K = X K ’Y K (B K + B K ’) + X K ’(Y K + Y K ’ ) B K + ( X K + X K ’)Y K B K
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
X K Y K B K D K B 0 0 0 0 0 0 0 1 1 1 K+1 0 1 0 1 1 D K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 B K+1 = B K = X K ’Y K xor X K + X K ’B K xor Y K + Y K B K
• The circuit expressions for the outputs are derived:
B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K = X K ’Y K (B K + B K ’) + X K ’(Y K + Y K ’ ) B K + ( X K + X K ’)Y K B K
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K
• These have the logic gate realizations:
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K
• These have the logic gate realizations:
B K X K Y K FS D K B K+1
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K Binary Full Subtractor
• These have the logic gate realizations:
Full Subtractor FS B K X K Y K FS D K B K+1 B K X K Y K D K B K+1
Circuit # 4 : Binary Subtractor
• We can now employ the 1-bit Full Subtractor to construct a multi bit subtractor – we use a FS with B 0 = 0 for the first bit. – this can be replaced with a specialized Half-Subtractor circuit.
B K X K Y K FS D K B K+1
Circuit # 4 : Binary Subtractor
• We can now employ the 1-bit Full Subtractor to construct a multi bit subtractor – we use a FS with B 0 = 0 for the first bit. (This can be replaced with a specialized Half-Subtractor circuit).
4-bit MSI: Ripple Subtractor Y 3 X 3 Y X B in B out S S 3 B out Y 2 X 2 Y X B in B out S S 2 Y 1 X 1 Y X B in B out S S 1 Y 0 X 0 0 Y X B in B out S S 0
Circuit # 4 : Binary Subtractor
bit subtractor – we use a FS with B 0
B Y 3 out Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0
= 0 for the first bit. This can be replaced with a
in D 0 4-bit MSI: Ripple Subtractor Y 3 X 3 Y X B in B out D D 3 B out Y 2 X 2 Y X B in B out D D 2 Y 1 X 1 Y X B in B out D D 1 Y 0 X 0 0 Y X B in B out D D 0
Circuit # 4 : Binary Subtractor
• Note that the Full Adder and Full Subtractor are identical, except for a single inverter applied to the first input (A or X):
C K X K Y K FA D K C K+1 B K X K Y K FS D K B K+1 C in A B Binary Full Adder FA S C out B K X K Y K Binary Full Subtractor Full Subtractor FS D K B K+1
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations.
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations.
• Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to
1
.
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations.
• Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to
1
.
Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 C out 4-bit MSI Full Ripple Adder C in 1 S 3 S 2 S 1 S 0
Circuit # 5 : Binary Adder/Subtractor
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate:
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = A
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = A Proof: 0 xor 0 = 0 1 xor 0 = 1
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = A Proof: 0 xor 0 = 0 1 xor 0 = 1 • These properties of the
xor
gate allow us to construct a circuit that can perform either addition or subtraction:
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
gate: A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = A Proof: 0 xor 0 = 0 1 xor 0 = 1 • These properties of the
xor
gate allow us to construct a circuit that can perform either addition or subtraction:
Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 4-bit MSI Full Ripple Adder/Subtractor Add(0)/ Sub(1) S 3 S 2 S 1 S 0
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the
xor
A xor 1 = A’ A xor 0 = A gate:
The input carry bit
Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’
choice of addition
Proof: 0 xor 0 = 0 1 xor 0 = 1 • These properties of the
xor
gate allow us to construct a circuit that can perform either addition or subtraction:
Y 3 Y 2 Y 1 Y 0 +/- +/- +/- +/ X 3 X 2 X 1 X 0 4-bit MSI Full Ripple Adder/Subtractor Add(0)/ Sub(1) S 3 S 2 S 1 S 0
Circuit # 5 : Binary Adder/Subtractor
• Now that it has been demonstrated that subtraction can be carried out using addition circuits, we may henceforth treat only addition cases, without any loss of generality.
Y 3 Y 2 Y 1 Y 0 +/- +/- +/- +/ X 3 X 2 X 1 X 0 4-bit MSI Full Ripple Adder/Subtractor S 3 S 2 S 1 S 0 Add(0)/ Sub(1)
Circuit # 6 : Carry Lookahead Adder
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K )
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K )
• Define terms:
g K = X K Y K
• We may now write:
C K+1 = g K + C K p K
and,
p K = (X K + Y K )
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K )
• Define terms:
g K = X K Y K
• We may now write: and,
p K = (X K + Y K ) C K+1 = g K + C K p K
• Also, recall that the sum bit is generated using the expression:
S K = C K xor A K xor B K
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
C K+1 = g K + C K p K S K = C K xor A K xor B K
We define the Sigma-block circuit:
P K G K X K Y K C K S K
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
C K+1 = g K + C K p K S K = C K xor A K xor B K
We define the Sigma-block circuit:
P K G K X K Y K C K
• This may be abbreviated as the MSI component:
X K Y K C K S K SIG P K G K S K
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
C K+1 S K
Note that both P
= g K
and G only require evaluation r
A K
r
B K P K X K Y K C K
We define the Sigma-block circuit:
G K
• This may be abbreviated as the MSI component:
X K Y K C K S K SIG P K G K S K
Circuit # 6 : Carry Lookahead Adder
• These results suggest that the previous ripple-adder circuit may be replaced by the following circuit, using Sigma-blocks:
Carry lookahead network C 0 C 4 P 3 G 3 X 3 Y 3 C 3 SIG S 3 P 2 G 2 X 2 Y 2 C 2 SIG S 2 P 1 G 1 X 1 Y 1 C 1 SIG S 1 P 0 G 0 X 0 Y 0 C 0 SIG S 0
Circuit # 6 : Carry Lookahead Adder
• Expanding the carry terms for a 4-bit adder:
C 1 = g 0 + C 0 p 0 C 2 = g 1 = g 1 + C 1 + (g 0 = g 1 + g 0 p 1 p + C 1 0 p 0 + C 0 )p p 0 1 p 1 C 3 = g 2 = g 2 + C + g 1 2 p p 2 2 + g 0 p 1 p 2 + C 0 p 0 p 1 p 2 C 4 = g 3 = g 3 + C + g 2 3 p p 3 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + C 0 p 0 p 1 p 2 p 3
Circuit # 6 : Carry Lookahead Adder
• Expanding the carry terms for a 4-bit adder:
C 1 = g 0 + C 0 p 0 C 2 = g 1 = g 1 + C 1 + (g 0 = g 1 + g 0 p 1 p + C 1 0 p 0 + C 0 )p p 0 1 p 1
Note that all the carry expressions require only two evaluation stages (one for the and, the other for the or).
C 3 = g 2 = g 2 + C + g 1 2 p p 2 2 + g 0 p 1 p 2 + C 0 p 0 p 1 p 2 C 4 = g 3 = g 3 + C + g 2 3 p p 3 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + C 0 p 0 p 1 p 2 p 3
Circuit # 6 : Carry Lookahead Adder
• These results can now be used to complete the Carry lookahead network portion of the 4-bit adder:
Carry lookahead network C 0 C 4 P 3 G 3 X 3 Y 3 C 3 SIG S 3 P 2 G 2 X 2 Y 2 C 2 SIG S 2 P 1 G 1 X 1 Y 1 C 1 SIG S 1 P 0 G 0 X 0 Y 0 C 0 SIG S 0
Circuit # 6 : Carry Lookahead Adder
• These results can now be used to complete the Carry lookahead network portion of the 4-bit adder:
Carry lookahead network C 0 C 4 P 3 G 3 C 3 P 2 G 2 C 2 P 1 G 1 C 1 P 0 G 0
Circuit # 6 : Carry Lookahead Adder
Now it is clear that network portion of the 4-bit adder: gates. Thus, each sum digit requires at most 4
Carry lookahead network
logic gates.
C 0 C 4 P 3 G 3 C 3 P 2 G 2 C 2 P 1 G 1 C 1 P 0 G 0
Circuit # 6 : Carry Lookahead Adder
• This brings us back to the basic, 4-bit MSI Adder/Subtractor, which may now be assumed to be optimized with carry lookahead circuits. • These may be used, in turn, to develop more powerful multi-bit adder/subtractors.
Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 C out 4-bit MSI Full Adder/Subtractor C in S 3 S 2 S 1 S 0 Add(0)/ Sub(1)
Circuit # 7 : Decimal Adder
Circuit # 7 : Decimal Adder
• There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421).
– BCD: 0 1 2 7 8 9 0000, 0001, 0010, … , 0111, 1000, 1001
Remind yourself that BCD uses a 4-bit representation to store the values of digits 0..9, but this leaves
wastage
of some bit patterns (unused patterns).
Circuit # 7 : Decimal Adder
• There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421).
– BCD: 0 1 2 7 8 9 0000, 0001, 0010, … , 0111, 1000, 1001 • To illustrate some of the issues we consider one example of decimal addition of single digits, leading to a full decimal adder.
– This design will be based on the use of the binary adder.
Circuit # 7 : Decimal Adder
• Note that the problem of adding two decimal digits together, in general, also requires accounting for an input carry and an output carry.
Minimum Sum:
0 (No carry) 0 + 0 0 (No Carry out) DECIMAL ARITHMETIC
Maximum Sum:
1 (Carry) 9 + 9 1 9 (Carry out)
• Note also that the maximum number of distinct sums is 20.
Circuit # 7 : Decimal Adder
Consider the example: general, also requires accounting for an input carry and an output carry.
Minimum Sum:
+ 99 ====
Maximum Sum:
0 (No carry) 0 + 0 0 1 (Carry) 9 + 9 1 9 DECIMAL ARITHMETIC (Carry out)
• Note that the maximum number of distinct sums is 20.
Circuit # 7 : Decimal Adder
• We can obtain the sums in two stages.
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0
• We can obtain the sums in two stages.
• First, list all possible
outputs
from the direct sum of the decimal digits, then …..
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
Direct sum of decimal digits, ranging from 0 to 19 10 , represented in 5 bit form with high order bit K.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0
• We can obtain the sums in two stages.
0 0 0 0 0 0 0 0 0 1
• First, list all possible outputs from the direct
0 0 0 1 1
with sum bits S J and carry-out bit C.
0 0 1 1 0 0 0 1 1 1
sum of the decimal digits, then …..
0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
• Beside each sum place the
expected
values of the sum bits and the carry out bit.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0
• The first-stage sums divide into two groups: – the first ten sums produce the
correct
final sum and carry bit patterns
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0
• The first-stage sums divide into two groups: – the first ten sums produce the correct final sum and carry bit patterns
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
– the last ten sums are all
incorrect
by the same amount, they should have 6 added to them to produce the correct final bit patterns.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0
• The first-stage sums divide into two groups: – the first ten sums produce the correct final sum and carry bit patterns
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
– the last ten sums are all incorrect by the same amount, they should have 6 added to them to produce the correct final bit patterns.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 + 6 = 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 + 6 = 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1
• The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C:
C = K + P 3
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 P 2 + P 3 P 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1
• The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C:
C = K + P 3
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 P 2 + P 3 P 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1
• Thus, if C = 0 then no correction is applied.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1
Circuit # 7 : Decimal Adder
K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0
• The condition used to
0 0 0 0 0 0 0 0 0 0
identify and control the correction process is expressed in terms of
0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1
the carry-out bit, C:
0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 C = K + P 3 P 2 + P 3 P 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1
• Thus, if C = 0 then no correction is applied.
0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 + 6 = 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1
• If C = 1 , then 6 is added directly to the initial sum bits P J .
1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 + 6 = 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1
Circuit # 7 : Decimal Adder
• The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C:
C out K A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C 4 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 4-bit binary adder s 3 s 2 s 1 s 0 C 0 P 3 P 2 P 1 P 0 C = K + P 3 P 2 + P 3 P 1 C in
• A decimal full-adder circuit follows using a two-stage 4-bit binary adder MSI circuit and • Uses the carry bit value directly to generate the value 6 10 , or 0110 2 .
0 Add 6 C 4 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 4-bit binary adder s 3 s 2 s 1 s 0 C 0 S 3 S 2 S 1 S 0
Circuit # 7 : Decimal Adder
• This MSI circuit is used to form the basis for a multi-decade decimal adder.
C out K A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C 4 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 4-bit binary adder s 3 s 2 s 1 s 0 C 0 P 3 P 2 P 1 P 0 C in A 3 C 4 x 3 A 2 A 1 A 0 B 3 B 2 B 1 Add 6 0 B 0 x 2 x 1 x 0 y 3 y 2 y 1 BCD Decade adder s 3 s 2 s 1 s 0 y 0 C 4 C 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 4-bit binary adder s 3 s 2 s 1 s 0 C 0 S 3 S 2 S 1 S 0 S 3 S 2 S 1 S 0
Time out for some Design Philosophy!
Time out for some Philosophy!
• In software design and construction the programmer/analyst becomes familiar with identifying different aspects of the problem in terms of abstract models. • Some of these models are quite concrete (bottom-up design) while others are relatively more abstract and require gradual expression of their detail (top-down design).
Time out for some Philosophy!
• Increasingly, modern Software Design is expressed in terms of components (functions, classes/objects, templates, metaprogramming) and focuses on software component re-use.
• One critical problem of software re-use lies in the proper, robust, flexible and standards-based design of the component interfaces.
• Other issues arise in the contexts of software complexity, performance, cost and other factors.
Time out for some Philosophy!
• Differential layering of abstraction in design also has its place in hardware design.
SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components • These differences have been demonstrated in each of the circuits/components that we have considered so far.
Time out for some Philosophy!
3 A 2 A 1 A 0 B 3 B 2 B 1 B 0
hardware design.
SSI K x 3 x 2 x 1 s 3 x 0 y 3 s 2 s 1 y 2 y 1
: Boolean algebra / Simplification / Logic gates
s 0 y 0 C 0 MSI: C in C out P P P P
Interconnection networks / Iterative re-use / Components • These differences have been demonstrated in each of the
Add 6
circuits/components that we have considered so far.
FA 0 C in A B S C 4 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 4-bit binary adder s 3 s 2 s 1 s 0 C 0 C out S 3 S 2 S 1 S 0
Circuit # 8 : Comparator
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable importance.
– if ( A < B ) then … – while ( A > B ) do ...
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable importance.
– if ( A < B ) then … – while ( A > B ) do ...
• It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions: A = B A > B A < B
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable importance.
– if ( A < B ) then … – while ( A > B ) do ...
• It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions: A = B A > B A < B These conditions may be encoded using 3 flag bits: E = 1 G = 1 L = 1
Circuit # 8 : Comparator
• One strategy is to perform the comparison
bit-wise
and from right to left.
Circuit # 8 : Comparator
• One strategy is to perform the comparison
bit-wise
and from right to left. • Express the two bit strings to be compared, A and B: A N … A K A K-1 … A 1 A 0 and B N … B K B K-1 … B 1 B 0
Circuit # 8 : Comparator
• One strategy is to perform the comparison
bit-wise
and from right to left. • Express the two bit strings to be compared, A and B: A N … A K A K-1 … A 1 A 0 and B N … B K B K-1 … B 1 B 0 • Now, restrict attention to the substrings: A K A K-1 … A 1 A 0 and B K B K-1 … B 1 B 0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1 , G K-1 = 0 , L K-1 = 0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 E K-1 = 1 , G K-1 = 0 , L K-1 = 0 E K-1 = 0 , G K-1 = 1 , L K-1 = 0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 1 , G K-1 = 0 , L K-1 = 0 E K-1 = 0 , G K-1 = 1 , L K-1 = 0 E K-1 = 0 , G K-1 = 0 , L K-1 = 1
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 1 , G K-1 = 0 , L K-1 = 0 E K-1 = 0 , G K-1 = 1 , L K-1 = 0 E K-1 = 0 , G K-1 = 0 , L K-1 = 1 • Note that only one of E K-1 , G K-1 or L K-1 may have value 1 at a time.
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 1 , G K-1 = 0 , L K-1 = 0 E K-1 = 0 , G K-1 = 1 , L K-1 = 0 E K-1 = 0 , G K-1 = 0 , L K-1 = 1 • Note that only one of E K-1 , G K-1 or L K-1 may have value 1 at a time.
• Our goal is to derive expressions for outputs E K , G K on the inputs A K , B K , E K-1 , G K-1 and L K-1 . and L K based
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0
•
Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0
Condition is not altered when
A K = B K
Condition is not altered when
A K = B K
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0
Condition L
K = 1
always applies when
A K < B K
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0
Condition G
K = 1
always applies when
A K > B K
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• This leads to Boolean expressions for the outputs (using don’t cares):
A K B K E K-1 G K-1 L K-1 E K G K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 G K = A K B K 0 1 0 1 0 0 0 1 E 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 L K K = A = A K K B B K K + A E K-1 + A K K G L K-1 + A K-1 K + B B K + B L K K K 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 E G K-1 L K-1 K-1
Circuit # 8 : Comparator
• The 1-bit comparator circuit is expressed:
A K B K G K-1 E K-1 L K-1 G K E K L K
Circuit # 8 : Comparator
• The 1- bit comparator circuit is expressed in MSI form:
G K E K L K A K B K 1-bit C o m p a r a r t o G K-1 E K-1 L K-1
Circuit # 8 : Comparator
• The 1- bit comparator circuit is expressed in MSI form:
As with previous circuits, the 1-bit comparator circuit can be extended to form multi-bit, MSI ripple comparators.
G K E K L K A K B K 1-bit C o m p a r a r t o G K-1 E K-1 L K-1 A K-1 B K-1 1-bit C o m p a r a r t o G K-2 E K-2 L K-2
Summary - Part II
• We continue to study logic design in the contexts of Small Scale Integration (SSI) and Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD).
• We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design.
Adders Subtractors Comparator • We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.) SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components