CHAPTER 2 Week 5 – 6
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Transcript CHAPTER 2 Week 5 – 6
CHAPTER 2:
DIGITAL ELECTRONICS WITH
MULTISIM
MultiSim: Arithmetic Circuits, Flip-flops,
Counters, Shift Registers and Multiplexers
Arithmetic Circuits
Arithmetic circuit perform mathematical
functions such as subtraction, multiplication,
and division.
Eg: adder circuits
Examples of adder ICs are:
7438N 4-bit binary adder
4008BT 4-bit full adder
Samjy/DENC 2533
Adder
Half adder:
The half adder accepts two binary digits on its inputs and
produces two binary digits on its outputs, a sum bit and a
carry bit.
Full Adder:
The full adder accepts two binary digits on its inputs and
input carry and generates a sum output and output carry.
Samjy/DENC 2533
HALF ADDER
1. LOGIC CIRCUIT
2. BOOLEON EXPRESSION
Sum, Σ = AB’ + A’B
= AB (XOR)
A
3. LOGIC DIAGRAM
COUT=AB (AND)
B
A
B
COUT
Σ
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
4. TRUTH TABLE
Samjy/DENC 2533
FULL ADDER
1. LOGIC CIRCUIT
A
2. BOOLEON EXPRESSION
B
Sum, Σ=(AB)CIN
Cin
COUT=AB+(AB)CIN
A
B
CIN
COUT
Σ
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
4. TRUTH TABLE
Samjy/DENC 2533
3. LOGIC DIAGRAM
Adder Circuits using 4008BT Full Adder
IC
U7
13
1
A3
8
S3
15
B3
12
3
A2
4
S2
2
B2
11
5
A1
J1
4
Data
Switch
7
B1
A0
2
S1
10
1
S0
6
B0
Key = S pace
14
9
CI N CO UT
4008BT
V1
5V
A3A2A1A0 + B3B2B1B0
Adder circuit to add 0110 and 0101 = 1011
Samjy/DENC 2533
16 (Carr y_Out)
Full Adder Circuit (2)
U3
13
1
A3
8
S3
15
B3
12
3
A2
4
S2
2
B2
11
5
A1
J1
4
Data
Switch
7
B1
A0
2
S1
10
1
S0
6
B0
Key = S pace
14
9
CIN CO UT
V1
16 (Carr y_out)
4008BT
5V
V DD
5V
A+B+Cin
Adding 8+9+1 carry input using full adder circuit
Samjy/DENC 2533
Binary Subtractor
Subtractor circuits take two binary numbers as input and subtract one
binary number input with other binary number input.
There are 4 basic rules for subtracting bits;
0–0=0
1–1=0
1–0=1
1 0–1=1
0 – 1 with a borrow of 1
Samjy/DENC 2533
EXAMPLE 2 :Subtract 100002 – 111012
SOLUTION :-
10000
- 111 01
10000
+ 00010 (1’C)
10010
No overflow
The answer is negative. The true magnitude is the 1’s complement of 10010
or 01101. The answer is -01101.
*Check.
1610 - 2910 = -1310
Samjy/DENC 2533
1st Complement Subtractor Circuits
Key = A
A1
Key = W
B1
Key = B
A2
Key = D
A4
1
16
3
4
8
7
10
11
13
14
C4 A4
15
S4 B4
A3
2
S3 B3
A2
6
S2 B2
A1
9
S1 B1
C0
Key = C
A3
Key = X
B2
74LS83N
Sub
Key = Y
B3
Key = Z
B4
Neg
1
V1
5V
Add
Key = Space
2
4
8
Carry Out
Samjy/DENC 2533
4 – 9 = -5
Sequential Circuit: Flip-Flops(ffs)
Is a logic circuit with a memory characteristics such that its output
(Q) will go to a new stage in response to an input pulse, and will
remain that new state after the input pulse is terminated.
Is a sequential circuit, whose output changes when its CLOCK input
triggers.
Several types of edge-triggered ffs, such as D, JK, SC ff.
Synchronous control input – ffs is synchronous with PGT/NGT
(positive/negative edge triggered) signal applied to CLOCK.
Asynchronous control input-set the ffs to ‘1’state or ‘0’ state by its 2
asynchronous inputs: PRESET and CLEAR.
Samjy/DENC 2533
Constructed of JK Flip-Flop Circuit using 74LS112N
IC
X SC1
R1
R2
R3
R4
X1
R5
X2
G
V3
A
U3A
5V
J3
J1
4
Key = P
3
~ 1PR
Key = J
1
Key = K
V1
6
2
J4
J5
5
1Q
1J
1K
~ 1Q
15
J2
~ 1CL R
Key = C
74LS 112N
Key = S pace
1000Hz 5V
J1 J2 J3 J4 J5 -
Preset (Key P)
Clear (Key C)
J Input (KeyJ)
K Input (KeyK)
Clock Input (Spacebar)
Samjy/DENC 2533
B
T
Sequential Circuit: Counters
Flip-flops and logic gates could be connected to function as
counters and registers.
Counters and related circuits may be used to count items, to time
functions, to synchronize various events, to divide, and to control
results based upon the outcome of a counting function.
The different types of counters are usually specified by their
activity and the type of output they provide.
Counters can be categorized as Up or Down counters.
Samjy/DENC 2533
Asynchronous and Synchronous
Counters
A synchronous counter circuit has the operation of flip-flops is
synchronized by a common clock pulse so that when several flip
flops must change state, the state changes occur simultaneously.
Asynchronous counters (Ripple counter) which the state change
of one flip flop triggers the next flip flop in line. It uses the
external event to directly SET or CLEAR a flip-flop when it
occurs. Each flip-flop in the ripple counter is clocked by the
output from the previous flip-flop. Only the first flip-flop is clocked
by an external clock.
Samjy/DENC 2533
Implementation with Different FF
Types
T flip-flops is well suited for straightforward binary counters -but yielded
worst gate and literal count
R-S flip-flops don't really exist.
J-K flip-flops yielded lowest gate count -tend to yield best choice for
reducing gate count in packaged logic
D flip-flops yield simplest design procedure -best choice where
area/literal count is the key.
Flip-flops excitation table
Samjy/DENC 2533
TYPES OF SYNCHRONOUS
COUNTER
Up counter.
- Counter that counts upward from 0
to a maximum count.
Down counter.
- Counter that counts from a maximum
count downward to 0.
Up / Down counter.
- Counter that can count up or down
depending on how its input are activated.
Samjy/DENC 2533
SYNCHRONOUS (Up Counter)
001
000
0
1
010
111
7
2
6
3
011
110
5
101
4
100
Samjy/DENC 2533
TRUTH TABLE
Present state
Next state
Flip-flop input
Q1
Q2
Q3
Q1
Q2
Q3
J1
K1
J2
K2
J3
K3
0
0
0
0
0
1
0
X
0
X
1
X
0
0
1
0
1
0
0
X
1
X
X
1
0
1
0
0
1
1
0
X
X
0
1
X
0
1
1
1
0
0
1
X
X
1
X
1
1
0
0
1
0
1
X
0
0
X
1
X
1
0
1
1
1
0
X
0
1
X
X
1
1
1
0
1
1
1
X
0
X
0
1
X
1
1
1
0
0
0
X
1
X
1
X
1
Samjy/DENC 2533
SCHEMATIC DIAGRAM
Samjy/DENC 2533
SYNCHRONOUS (Down Counter)
111
110
6
7
000
101
5
0
4
1
001
100
3
011
2
010
Samjy/DENC 2533
TRUTH TABLE
Present state
Next state
Flip-flop input
Q1
Q2
Q3
Q1
Q2
Q3
J1
K1
J2
K2
J3
K3
0
0
0
1
1
1
X
0
X
0
X
1
0
0
1
1
1
0
X
0
X
1
1
X
0
1
0
1
0
1
X
0
0
X
X
1
0
1
1
1
0
0
X
1
1
X
1
X
1
0
0
0
1
1
0
X
X
0
X
1
1
0
1
0
1
0
0
X
X
1
1
X
1
1
0
0
0
1
0
X
0
X
X
1
1
1
1
0
0
0
1
X
1
X
1
X
Samjy/DENC 2533
SCHEMATIC DIAGRAM
Samjy/DENC 2533
Asynchronous (Ripple Counter)
X SC1
G
A
X1
V2
X2
T
B
X3
5V
X LA1
U1A
14
U1B
12
1J
7
1Q
9
2J
1
U3A
14
2Q
5
1
12
1J
1Q
1K
~1Q
1
V1
3
13
1K
8kHz 5V
2K
74LS 73N
2
~1CLR
10
~1Q
6
~2CLR
8
3
74LS 73N
2
~2Q
13
74LS 73N
~1CLR
F
C Q
Samjy/DENC 2533
T
74LS293: 4-STAGE IC ASYNCRONOUS
COUNTER
X SC1
U3
G
A
B
T
NOT
X LA1
U1
9
10
A
QA
B
QB
11
V1
14kHz 5V
1
5
12
R0(1) Q C
13
4
8
R0(2) Q D
74LS 293N
U2
AND3
F
C Q
T
Example of circuit using IC for 4-stage asynchronous counter.
This circuit uses the 74LS293 as a MOD-14 Counter.
Samjy/DENC 2533
The Synchronous Counter
X SC1
G
A
X1
X2
U1A
14
7
1J
1
U2A
14
9
2Q
2J
5
3
13
~1CLR
1Q
1K
~1Q
3
8
~2Q
2K
74LS 73N
2
12
1J
1
10
~1Q
1K
T
X3
U1B
12
1Q
B
74LS 73N
6
~2CLR
13
74LS 73N
2
~1CLR
V1
V3
1
5V
2
U6A
3
24kHz 5V
74LS 08N
3-stage synchronous counter
A synchronous counter is a counter whose ffs are clocked simultaneously by a common clock source.
The synchronization of the clocking event causes the transitions of all of the ffs states to occur
simultaneously.
IC: 74LS393N synchronous counter
Samjy/DENC 2533
Sequential Circuit: Shift Registers
Shift registers circuits are synchronous digital circuits used to store or
move binary data.
These types of circuits consist either of a series of FFs in groups which
can store one bit of data each or as shift register ICs that store larger
groups of data.
The amount of data that can be stored in a shift register depends on the
width of the register and the number of storage FFs contained in the
register.
Basic method of shift registers:
Serial in/serial out shift register
Serial in/ parallel out
Parallel in/serial out
Parallel in/parallel out
Samjy/DENC 2533
Serial In/Serial Out Shift Registers
X1
X2
X3
X4
Preset
4
10
~ 1PR
5V
S3
Key = D
D ata
In
5
2
1
S2
Key = S pace
S1
9
11
8
3
1
2Q
2D
6
~ 1Q
9
12
1Q
1D
~ 2Q
13
~ 2PR
5
2
2Q
2D
6
~ 1Q
10
~ 1PR
12
1Q
1D
3
4
~ 2PR
11
8
~ 2Q
13
~ 1CL R
~ 2CL R
~ 1CL R
~ 2CL R
74LS 74N
74LS 74N
74LS 74N
74LS 74N
C lock
C lear
Key = C
Samjy/DENC 2533
Serial
D ata Out
Serial In/Parallel Out Shift Registers
X1
X2
X3
X4
A
B
C
D
Preset
4
10
~ 1PR
5V
S3
Key = D
D ata
In
5
2
Key = S pace
S1
9
11
13
~ 1Q
1
2Q
2D
6
3
9
12
1Q
1D
8
~ 2Q
~ 2PR
5
2
2Q
2D
6
~ 1Q
1
S2
10
~ 1PR
12
1Q
1D
3
4
~ 2PR
11
8
~ 2Q
13
~ 1CL R
~ 2CL R
~ 1CL R
~ 2CL R
74LS 74N
74LS 74N
74LS 74N
74LS 74N
C lock
C lear
Key = C
Samjy/DENC 2533
Paral lel
D ata Out
Multiplexer
a) Multiplexer digital atau pemilih data adalah litar logik yang menerima
beberapa data masukan digital dan memilih satu daripadanya pada
bila-bila masa untuk dihantar ke keluaran.
b) Kitaran data masukan yang diperlukan oleh keluaran adalah dikawal
oleh masukan SELECT (biasanya dikenali sebagai alamat masukan).
MULTIPLEXER
2-MASUKAN
MULTIPLEXER
4-MASUKAN
MULTIPLEXER
Samjy/DENC 2533
8-MASUKAN
MULTIPLEXER
a. Mempunyai data masukan
I0 dan I1 dan masukan
SELECT “S”.
b. Z = I0 S’ + I1S
Samjy/DENC 2533
S
OUTPUT
0
I1
1
I0
S
Samjy/DENC 2533
OUTPUT
0
0
I0
0
1
I1
1
0
I2
1
1
I3
4-to-1 Mux Using 2-to-1 Mux in Multisim
Samjy/DENC 2533
a. Enable akan menghasilkan samada keluaran normal atau sebaliknya.
b. Jika enable (E’)=0, maka S2,S1 dan S0 akan memilih salah satu daripada
data masukan dari I0 hingga I7.
c. Jika enable (E’)=1 multiplexer tidak akan berfungsi yang mana Z=0 dan
mengabaikan masukan SELECT.
Samjy/DENC 2533
What is Demultiplexer ?
Demultiplexer is known as data
distributors.
It performs the reverse operation of
multiplexer.
It takes input and distributes it over
several outputs.
Samjy/DENC 2533
Demultiplexer
LOGIC DIAGRAM
DEMUX
O0
O1
Data
Input
ON-1
SELECT Input
Samjy/DENC 2533
DATA input
transmitted to only one
of the outputs as
determined by select
input code.
A one-to-two-line demultiplexer is shown
below
Clock
Output
Switch
S
Samjy/DENC 2533
1-to-4 line Demultiplexer
Data
input
Select Lines
Data
output
lines
Samjy/DENC 2533
1-to-16 Demux using 74HC154NT: in Multisim
Samjy/DENC 2533